参数资料
| 型号： | AD7195BCPZ-RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 27/45页 |
| 文件大小： | 0K |
| 描述： | IC AFE 24BIT 4.8K 32LFSP |
| 设计资源： | Precision Weigh Scale Design Using AD7195 with Internal PGA and AC Excitation (CN0155) |
| 标准包装： | 1,500 |
| 位数： | 24 |
| 通道数： | 4 |
| 电压 - 电源，模拟： | 4.75 V ~ 5.25 V |
| 电压 - 电源，数字： | 2.7 V ~ 5.25 V |
| 封装/外壳： | 32-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-WQ（5x5） |
| 包装： | 带卷 (TR) |
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AD7195
Rev. 0 | Page 32 of 44
RESET
The circuitry and serial interface of the AD7195 can be reset
by writing consecutive 1s to the device; 40 consecutive 1s are
required to perform the reset. This resets the logic, the digital
filter, and the analog modulator, whereas all on-chip registers
are reset to their default values. A reset is automatically
performed on power-up. When a reset is initiated, the user
must allow a period of 500 μs before accessing any of the
on-chip registers. A reset is useful if the serial interface loses
synchronization due to noise on the SCLK line.
SYSTEM SYNCHRONIZATION
The SYNC input allows the user to reset the modulator and the
digital filter without affecting any of the setup conditions on
the part. This allows the user to start gathering samples of the
analog input from a known point in time, that is, the rising edge
of SYNC. SYNC needs to be taken low for at least four master
clock cycles to implement the synchronization function.
If multiple AD7195 devices operate from a common master
clock, they can be synchronized so that their data registers are
updated simultaneously. A falling edge on the SYNC pin resets
the digital filter and the analog modulator and places the AD7195
into a consistent, known state. While the SYNC pin is low, the
AD7195 is maintained in this state. On the SYNC rising edge,
the modulator and filter are taken out of this reset state and, on
the next clock edge, the part starts to gather input samples again.
In a system using multiple AD7195 devices, a common signal to
their SYNC pins synchronizes their operation. This is normally
done after each AD7195 has performed its own calibration or
has calibration coefficients loaded into its calibration registers.
The conversions from the AD7195s are then synchronized.
The part is taken out of reset on the master clock falling edge
following the SYNC low to high transition. Therefore, when
multiple devices are being synchronized, the SYNC pin should
be taken high on the master clock rising edge to ensure that all
devices begin sampling on the master clock falling edge. If the
SYNC pin is not taken high in sufficient time, a difference of
one master clock cycle may result between the devices; that is,
the instant at which conversions are available differs from part
to part by a maximum of one master clock cycle.
The SYNC pin can also be used as a start conversion command.
In this mode, the rising edge of SYNC starts conversion, and the
falling edge of RDY indicates when the conversion is complete.
The settling time of the filter has to be allowed for each data
register update. For example, if the ADC is configured to use
the sinc4 filter, zero latency is disabled, and chop is disabled, the
settling time equals 4/fADC where fADC is the output data rate
when continuously converting on a single channel.
CLOCK
The AD7195 includes an internal 4.92 MHz clock on-chip. This
internal clock has a tolerance of ±4%. Either the internal clock
or an external crystal/clock can be used as the clock source to
the AD7195. The clock source is selected using the CLK1 and
CLK0 bits in the mode register. When an external crystal is
used, it must be connected across the MCLK1 and MCLK2
pins. The crystal manufacturer recommends the load capacitances
required for the crystal. The MCLK1 and MCLK2 pins of the
AD7195 have a capacitance of 15 pF, typically. If an external
clock source is used, the clock source must be connected to the
MCLK2 pin, and the MCLK1 pin can be left floating.
The internal clock can also be made available at the MCLK2
pin. This is useful when several ADCs are used in an application
and the devices must be synchronized. The internal clock from
one device can be used as the clock source for all ADCs in the
system. Using a common clock, the devices can be synchro-
nized by applying a common reset to all devices, or the SYNC
pin can be pulsed.
ENABLE PARITY
The AD7195 also has an on-chip parity check function that
detects 1-bit errors in the serial communications between
the ADC and the microprocessor. When the ENPAR bit in
the mode register is set to 1, parity is enabled. The contents of
the status register must be transmitted along with each 24-bit
conversion when the parity function is enabled. To append the
contents of the status register to each conversion read, the
DAT_STA bit in the mode register should be set to 1.
For each conversion read, the parity bit in the status register is
programmed so that the overall number of 1s transmitted in the
24-bit data-word is even. Therefore, for example, if the 24-bit
conversion contains eleven 1s (binary format), the parity bit is
set to 1 so that the total number of 1s in the serial transmission
is even. If the microprocessor receives an odd number of 1s, it
knows that the data received has been corrupted.
The parity function only detects 1-bit errors. For example, two
bits of corrupt data can result in the microprocessor receiving an
even number of 1s. Therefore, an error condition is not detected.
TEMPERATURE SENSOR
Embedded in the AD7195 is a temperature sensor. This is
selected using the CH2 bit in the configuration register. When
the CH2 bit is set to 1, the temperature sensor is enabled. When
the temperature sensor is selected and bipolar mode is selected,
the device should return a code of 0x800000 when the temper-
ature is 0 K. A one-point calibration is needed to get the optimum
performance from the sensor. Therefore, a conversion at 25°C
should be recorded and the sensitivity calculated. The sensitivity
is approximately 2815 codes/°C. The equation for the temperature
sensor is
Temp (K) = (Conversion 0x800000)/2815 K
Temp (°C) = Temp (K) 273
Following the one point calibration, the internal temperature
sensor has an accuracy of ±2 °C, typically.
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