参数资料
型号: AD7719BRUZ
厂商: Analog Devices Inc
文件页数: 24/40页
文件大小: 0K
描述: IC ADC 16BIT 24BIT DUAL 28-TSSOP
标准包装: 50
位数: 16/24
采样率(每秒): 105
数据接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 2
功率耗散(最大): 4.5mW
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 28-TSSOP
包装: 管件
输入数目和类型: 3 个差分,单极;3 个差分,双极
产品目录页面: 778 (CN2011-ZH PDF)
REV. A
AD7719
–30–
AD7719-to-ADSP-2103/ADSP-2105 Interface
Figure 14 shows an interface between the AD7719 and the
ADSP-2103/ADSP-2105 DSP processor. In the interface shown,
the RDY bits of the Status register are again monitored to
determine when the Data register is updated. The alternative
scheme is to use an interrupt-driven system, in which case the
RDY output is connected to the IRQ2 input of the ADSP-2103/
ADSP-2105. The serial interface of the ADSP-2103/ADSP-2105
is set up for alternate framing mode. The
RFS and TFS pins
of the ADSP-2103/ADSP-2105 are configured as active low
outputs and the ADSP-2103/ADSP-2105 serial clock line, SCLK,
is also configured as an output. The
CS for the AD7719 is active
when either the
RFS or TFS outputs from the ADSP-2103/
ADSP-2105 are active. The serial clock rate on the ADSP-2103/
ADSP-2105 should be limited to 3 MHz to ensure correct opera-
tion with the AD7719.
RESET
DVDD
CS
AD7719
SCLK
DT
DR
RFS
TFS
ADSP-2103 /
ADSP-2105
DIN
DOUT
Figure 14. AD7719-to-ADSP-2103/ADSP-2105 Interface
CIRCUIT DESCRIPTION
The AD7719 is a
Σ- A/D converter incorporating two indepen-
dent
Σ- A/D converters with on-chip digital filtering, intended
for the measurement of wide dynamic range, low frequency
signals such as those in weigh scale, pressure, temperature,
industrial control, or process control applications.
The main ADC is intended to convert the primary sensor input.
The main ADC employs a
Σ- conversion technique to realize up
to 24 bits of no-missing-codes performance. The
Σ- modulator
converts the sampled input signal into a digital pulse train whose
duty cycle contains the digital information. A Sinc
3 programmable
low-pass filter is then employed to decimate the modulator output
data stream to give a valid data conversion result at program-
mable output rates from 5.35 Hz (186.77 ms) to 105.03 Hz
(9.52 ms). A Chopping scheme is also employed to minimize
ADC offset and offset and gain drift errors. The analog input
to the main ADC can be operated in buffered or unbuffered
mode and can be programmed for one of eight input ranges from
±20 mV to ±2.56 V. The input channels can be configured for
either fully differential inputs or pseudodifferential input
channels via the CH1 and CH0 bits in the main ADC control
register (AD0CON) and the CHCON bit in the mode register.
When configured for buffered mode (
BUF = 0), the input channels
are internally buffered, allowing the part to handle significant
source impedances on the analog input, allowing R/C filtering
(for noise rejection or RFI reduction) to be placed on the analog
inputs if required. When operating in unbuffered mode, care has
to be exercised when selecting front end source impedances so
as not to introduce gain errors. On-chip burnout currents are
available and can be used to check that a transducer on the
selected channel is still operational before attempting to take
measurements.
The second or auxiliary ADC is intended to convert secondary
inputs such as those from a cold junction diode or thermistor.
This ADC is unbuffered and has a fixed input range of 0 V
to REFIN2 (ARN bit = 1) or 0 to REFIN2/2 (ARN bit = 0).
Again, this ADC can be configured for differential or pseudo-
differential inputs via the ACH2, ACH1, and ACH0 bits in the
auxiliary ADC control register (AD1CON). The auxiliary ADC
is specified for 16-bit performance and, since its analog inputs
are unbuffered, care must be exercised when placing filtering on
the front end to avoid introducing gain errors into the measure-
ment system.
The basic connection diagram for the AD7719 is shown in
Figure 15. This shows both the AVDD and DVDD pins of the
AD7719 being driven from the analog 5 V supply. Some appli-
cations will have AVDD and DVDD driven from separate supplies.
AVDD and DVDD can be operated independently of each other,
allowing the device to be operated with 5 V analog supply and
3 V digital supply or vice versa. An AD780/REF195 precision
2.5 V reference provides the reference source for the part. A
quartz crystal or ceramic resonator provides the 32 kHz master
clock source for the part. In some cases, it will be necessary to
connect capacitors on the crystal or resonator to ensure that it
does not oscillate at overtones of its fundamental operating
frequency. The values of capacitors will vary depending on the
manufacturer’s specifications.
AD780/
REF195
XTAL1
XTAL2
RECEIVE
(READ)
P1/SW1
P2/SW2
P3
P4
0.1 F
10 F
ANALOG 5V
SUPPLY
GND
VIN
VOUT
PWRGND
AGND
DGND
0.1 F
10 F
0.1 F
AVDD
DVDD
IOUT1
IOUT2
AIN1
AIN2
AIN3
AIN4
AIN5
REFIN2
REFIN1(+)
REFIN1(–)
AIN6
RESET
CS
DOUT
DIN
SCLK
5V
CHIP
SELECT
SERIAL
DATA
(WRITE)
SERIAL
CLOCK
32kHz
CRYSTAL
ANALOG 5V
SUPPLY
AD7719
Figure 15. Basic Connection Diagram
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