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参数资料
| 型号： | AD7731BRZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 20/44页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT SIGMA-DELTA 24-SOIC |
| 标准包装： | 1,000 |
| 位数： | 24 |
| 采样率（每秒）： | 6.4k |
| 数据接口： | DSP，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 125mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 24-SOIC W |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 3 个差分，单极；3 个差分，双极；5 个伪差分，单极；5 个伪差分，双极 |
| 配用： | EVAL-AD7731EBZ-ND - BOARD EVALUATION FOR AD7731 |
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AD7731
–27–
REV. 0
Nonchop Mode (SKIP = 0, CHP = 0)
With CHOP mode disabled and SKIP mode disabled, the only
function of the second stage filter is to give the overall frequency
response. Figure 11 shows the frequency response for the AD7731
with the second stage filter is set for normal FIR operation, chop
mode disabled, the decimal equivalent of the word in the SF bits
set to 1536 and a master clock frequency of 4.9152 MHz. The
response is analogous to that of Figure 9 with the three-times
larger SF word producing the same 200 Hz output rate. Once
again, the response will scale proportionally with master clock
frequency. The response is shown from dc to 100 Hz. The re-
jection at 50 Hz
± 1 Hz and 60 Hz ± 1 Hz is better than 88 dB.
The –3 dB frequency for the frequency response of the AD7731
with the second stage filter set for normal FIR operation and
chop mode enabled is determined by the following relationship:
f
3 dB = 0. 039 × f MOD ×
1
SF
CHP
= 0
()
In this case, f3 dB = 7.8 Hz and the stop-band, where the attenu-
ation is greater than 64.5 dB, is determined by:
f
STOP = 0.14 × f MOD ×
1
SF
CHP
= 0
()
In this case, fSTOP = 28 Hz.
FREQUENCY – Hz
0
–60
–100
090
GAIN
–
dB
10
20
30
40
50
60
70
80
–10
–50
–70
–90
–30
–40
–80
–20
–120
–110
100
Figure 11. Detailed Full Frequency Response of AD7731
(SKIP = 0, CHP = 0, SF = 1536)
Figure 12 shows the frequency response for the same set of
conditions as for Figure 11 but in this case the response in shown
out to 600 Hz. This plot is comparable to that of Figure 10. The
most notable difference is absence of the peaks in the response
at 200 Hz and 400 Hz. As a result, interference at these fre-
quencies will be effectively eliminated before being aliased back
to dc.
Table XVIII summarizes the settling time and subsequent through-
put rate for the various different modes.
FREQUENCY – Hz
0
–60
–100
0
450
GAIN
–
dB
50
100 150 200 250 300 350 400
–10
–50
–70
–90
–30
–40
–80
–20
–120
–110
500 550
600
Figure 12. Expanded Full Frequency Response of AD7731
(SKIP = 0, CHP = 0, SF = 1536)
REV. A
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| AD7731BRZ-REEL7 | 功能描述:IC ADC 24BIT SIGMA-DELTA 24-SOIC RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:12 采样率（每秒）:300k 数据接口:并联 转换器数目:1 功率耗散（最大）:75mW 电压电源:单电源 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC 包装:带卷 (TR) 输入数目和类型:1 个单端，单极；1 个单端，双极 |
| AD7731EB | 制造商:AD 制造商全称:Analog Devices 功能描述:Low Noise High Throughput 24-Bit Sigma-Delta ADC(411.99 k) |
| AD7732 | 制造商:AD 制造商全称:Analog Devices 功能描述:2-Channel, +-10 V Input Range, High Throughput, 24-Bit SIGMA- ADC |
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