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| 型号： | AD7731BRZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 34/44页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT SIGMA-DELTA 24-SOIC |
| 标准包装： | 1,000 |
| 位数： | 24 |
| 采样率（每秒）： | 6.4k |
| 数据接口： | DSP，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 125mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 24-SOIC W |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 3 个差分，单极；3 个差分，双极；5 个伪差分，单极；5 个伪差分，双极 |
| 配用： | EVAL-AD7731EBZ-ND - BOARD EVALUATION FOR AD7731 |
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AD7731
–4–
REV. 0
NOTES
1 Temperature Range: –40
°C to +85°C.
2 Sample tested during initial release.
3 No missing codes performance with CHP = 0 and SKIP = 1 is 22 bits.
4 The offset (or zero) numbers with CHP = 0 can be up to 1 mV precalibration. Internal zero-scale calibration reduces this to 2
V typical. Offset numbers with CHP = 1 are typically
3
V precalibration. Internal zero-scale calibration reduces this by about 1 V. System zero-scale calibration reduces offset numbers with CHP = 0 and CHP = 1 to the order of the
noise. Gain errors can be up to 3000 ppm precalibration with CHP = 0 and CHP = 1. Performing internal full-scale calibrations on all input ranges except the 20 mV and 40 mV input
range reduces the gain error to less than 100 ppm. When operating on the 20 mV or 40 mV range, an internal full-scale calibration should be performed on the 80 mV input range with
a resulting gain error of less than 250 ppm. System full-scale calibration reduces the gain error on all input ranges to the order of the noise. Positive and Negative Full-Scale Errors can
be calculated from the offset and gain errors.
5 These numbers are generated during life testing of the part.
6 Positive Full-Scale Error includes Zero-Scale Errors (Unipolar Offset Error or Bipolar Zero Error) and applies to both unipolar and bipolar input ranges. See Terminology.
7 Recalibration at any temperature will remove these errors.
8 Full-scale drift includes Zero-Scale Drift (Unipolar Offset Drift or Bipolar Zero Drift) and applies to both unipolar and bipolar input ranges.
9 Gain Error is a measure of the difference between the measured and the ideal span between any two points in the transfer function. The two points use to calculate the gain error are
positive full-scale and negative full-scale. See Terminology.
10 Gain Error Drift is a span drift and is effectively the drift of the part if zero-scale calibrations only were performed.
11 Power Supply Rejection and Common-Mode Rejection are given here for the upper and lower input voltage ranges. The rejection can be approximated to varying linearly (in dBs)
between these values for the other input ranges.
12 The analog input voltage range on the AIN(+) inputs is given here with respect to the voltage on the respective AIN(–) input.
13 The common-mode voltage range on the input pairs applies provided the absolute input voltage specification is obeyed.
14 The common-mode voltage range on the reference input pair (REF IN(+) and REF IN(–)) applies provided the absolute input voltage specification is obeyed.
15 These logic output levels apply to the MCLK OUT output only when it is loaded with a single CMOS load.
16 V
DD refers to DVDD for all logic outputs expect D0 and D1 where it refers to AVDD. In other words, the output logic high for these two outputs is determined by AVDD.
17 See Burnout Current section.
18 After calibration, if the input voltage exceeds positive full scale, the converter will output all 1s. If the input is less than negative full scale, then the device outputs all 0s.
19 These calibration and span limits apply provided the absolute input voltage specification is obeyed. The offset calibration limit applies to both the unipolar zero point and the bipolar
zero point.
Specifications subject to change without notice.
TIMING CHARACTERISTICS1, 2
Limit at TMIN, TMAX
Parameter
(B Version)
Units
Conditions/Comments
Master Clock Range
1
MHz min
For Specified Performance
5
MHz max
t1
50
ns min
SYNC Pulse Width
t2
50
ns min
RESET Pulse Width
Read Operation
t3
0
ns min
RDY to CS Setup Time
t4
0
ns min
CS Falling Edge to SCLK Active Edge Setup Time3
t5
4
0
ns min
SCLK Active Edge to Data Valid Delay
60
ns max
DVDD = +4.75 V to +5.25 V
80
ns max
DVDD = +2.7 V to +3.3 V
t5A
0
ns min
CS Falling Edge to Data Valid Delay3
60
ns max
DVDD = +4.75 V to +5.25 V
80
ns max
DVDD = +2.7 V to +3.3 V
t6
100
ns min
SCLK High Pulse Width
t7
100
ns min
SCLK Low Pulse Width
t8
0
ns min
CS Rising Edge to SCLK Inactive Edge Hold Time3
10
ns min
Bus Relinquish Time after SCLK Inactive Edge
80
ns max
t10
100
ns max
SCLK Active Edge to
RDY High3, 7
Write Operation
t11
0
ns min
CS Falling Edge to SCLK Active Edge Setup Time3
t12
30
ns min
Data Valid to SCLK Edge Setup Time
t13
25
ns min
Data Valid to SCLK Edge Hold Time
t14
100
ns min
SCLK High Pulse Width
t15
100
ns min
SCLK Low Pulse Width
t16
0
ns min
CS Rising Edge to SCLK Edge Hold Time
NOTES
1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV
DD) and timed from a voltage level of 1.6 V.
2 See Figures 15 and 16.
3 SCLK active edge is falling edge of SCLK with POL = 1; SCLK active edge is rising edge of SCLK with POL = 0.
4 These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V
OL or VOH limits.
5 This specification only comes into play if
CS goes low while SCLK is low (POL = 1) or if CS goes low while SCLK is high (POL = 0). It is required primarily for interfacing to
DSP machines.
6 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapo-
lated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the
part and as such are independent of external bus loading capacitances.
7
RDY returns high after the first read from the device after an output update. The same data can be read again, if required, while RDY is high, although care should be taken that
subsequent reads do not occur close to the next output update.
(AVDD = +4.75 V to +5.25 V; DVDD = +2.7 V to +5.25 V; AGND = DGND = 0 V;
fCLK IN = 4.9152 MHz; Input Logic 0 = 0 V, Logic 1 = DVDD unless otherwise noted)
REV. A
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