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参数资料
| 型号： | AD7731BRZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/44页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT SIGMA-DELTA 24-SOIC |
| 标准包装： | 1,000 |
| 位数： | 24 |
| 采样率（每秒）： | 6.4k |
| 数据接口： | DSP，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 125mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 24-SOIC W |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 3 个差分，单极；3 个差分，双极；5 个伪差分，单极；5 个伪差分，双极 |
| 配用： | EVAL-AD7731EBZ-ND - BOARD EVALUATION FOR AD7731 |
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AD7731
–16–
REV. 0
MD2
MD1
MD0
Operating Mode
0
Sync (Idle) Mode. In this mode, the modulator and filter are held in reset mode and the AD7731 is not
processing any new samples or data. Placing the part in this mode is equivalent to exerting the
SYNC
input pin. However, exerting the
SYNC does not actually force these mode bits to 0, 0, 0. The part re-
turns to this mode after a calibration or after a conversion in Single Conversion Mode. This is the default
condition of these bits after Power-On/Reset.
0
1
Continuous Conversion Mode. In this mode, the AD7731 is continuously processing data and providing
conversion results to the Data Register at the programmed output update rate (as determined by the
Filter Register). For most applications, this would be the normal operating mode of the AD7731.
0
1
0
Single Conversion Mode. In this mode, the AD7731 performs a single conversion, updates the Data
Register, returns to the Sync Mode and resets the mode bits to 0, 0, 0. The result of the single conversion
on the AD7731 in this mode will not be provided until the full settling-time of the filter has elapsed.
0
1
Power-Down (Standby) Mode. In this mode, the AD7731 goes into its power-down or standby state. Placing
the part in this mode is equivalent to exerting the
STANDBY input pin. However, exerting STANDBY does
not actually force these mode bits to 0, 1, 1.
1
0
Zero-Scale Self-Calibration Mode. This activates zero-scale self-calibration on the channel selected by the
CH2, CH1 and CH0 bits of the Mode Register. This zero-scale self-calibration is performed at the se-
lected gain on internally shorted (zeroed) inputs. When this zero-scale self-calibration is complete, the
part updates the contents of the Offset Calibration Register and returns to Sync Mode with MD2, MD1
and MD0 returning to 0, 0, 0. The
RDY output and bit go high when calibration is initiated and return
low when this zero-scale self-calibration is complete to indicate that the part is back in Sync Mode and
ready for further operations.
1
0
1
Full-Scale Self-Calibration Mode. This activates full-scale self-calibration on the channel selected by the
CH2, CH1 and CH0 bits of the Mode Register. This full-scale self-calibration is performed at the se-
lected gain on an internally-generated full-scale signal. When this full-scale self-calibration is complete,
the part updates the contents of the Gain Calibration Register and returns to Sync Mode with MD2,
MD1 and MD0 returning to 0, 0, 0. The
RDY output and bit go high when calibration is initiated and
return low when this full-scale self-calibration is complete to indicate that the part is back in Sync Mode
and ready for further operations.
1
0
Zero-Scale System Calibration Mode. This activates zero scale system calibration on the channel selected
by the CH2, CH1 and CH0 bits of the Mode Register. Calibration is performed at the selected gain on
the input voltage provided at the analog input during this calibration sequence. This input voltage should
remain stable for the duration of the calibration. When this zero-scale system calibration is complete, the
part updates the contents of the Offset Calibration Register and returns to Sync Mode with MD2, MD1
and MD0 returning to 0, 0, 0. The
RDY output and bit go high when calibration is initiated and return
low when this zero-scale calibration is complete to indicate that the part is back in Sync Mode and ready
for further operations.
1
Full-Scale System Calibration Mode. This activates full-scale system calibration on the selected input
channel. Calibration is performed at the selected gain on the input voltage provided at the analog input
during this calibration sequence. This input voltage should remain stable for the duration of the calibra-
tion. When this full-scale system calibration is complete, the part updates the contents of the Gain Cali-
bration Register and returns to Sync Mode with MD2, MD1 and MD0 returning to 0, 0, 0. The
RDY
output and bit go high when calibration is initiated and return low when this full-scale calibration is com-
plete to indicate that the part is back in Sync Mode and ready for further operations.
REV. A
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相关代理商/技术参数 |
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