参数资料
| 型号： | AD7891YPZ-1 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/20页 |
| 文件大小： | 0K |
| 描述： | IC DAS 12BIT 8CH 44-PLCC |
| 标准包装： | 1 |
| 类型： | 数据采集系统（DAS） |
| 分辨率（位）： | 12 b |
| 采样率（每秒）： | 500k |
| 数据接口： | 串行，并联 |
| 电压电源： | 单电源 |
| 电源电压： | 5V |
| 工作温度： | -55°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-LCC（J 形引线） |
| 供应商设备封装： | 44-PLCC（16.59x16.59） |
| 包装： | 管件 |
AD7891
–4–
REV. D
TIMING CHARACTERISTICS1, 2
Parameter
A, B, Y Versions
Unit
Test Conditions/Comments
tCONV
1.6
ms max
Conversion Time
Parallel Interface
t1
0
ns min
CS to RD/WR Setup Time
t2
35
ns min
Write Pulse Width
t3
25
ns min
Data Valid to Write Setup Time
t4
5
ns min
Data Valid to Write Hold Time
t5
0
ns min
CS to RD/WR Hold Time
t6
35
ns min
CONVST Pulse Width
t7
55
ns min
EOC Pulse Width
t8
35
ns min
Read Pulse Width
t9
3
25
ns min
Data Access Time after Falling Edge of
RD
t10
4
5
ns min
Bus Relinquish Time after Rising Edge of
RD
30
ns max
Serial Interface
t11
30
ns min
RFS Low to SCLK Falling Edge Setup Time
t12
3
20
ns max
RFS Low to Data Valid Delay
t13
25
ns min
SCLK High Pulse Width
t14
25
ns min
SCLK Low Pulse Width
t15
3
5
ns min
SCLK Rising Edge to Data Valid Hold Time
t16
3
15
ns max
SCLK Rising Edge to Data Valid Delay
t17
20
ns min
RFS to SCLK Falling Edge Hold Time
t18
4
0
ns min
Bus Relinquish Time after Rising Edge of
RFS
30
ns max
t18A
4
0
ns min
Bus Relinquish Time after Rising Edge of SCLK
30
ns max
t19
20
ns min
TFS Low to SCLK Falling Edge Setup Time
t20
15
ns min
Data Valid to SCLK Falling Edge Setup Time
t21
10
ns min
Data Valid to SCLK Falling Edge Hold Time
t22
30
ns min
TFS Low to SCLK Falling Edge Hold Time
NOTES
1Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 1 ns (10% to
90% of 5 V) and timed from a voltage level of 1.6 V.
2See Figures 2, 3, and 4.
3Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
Specifications subject to change without notice.
1.6mA
200 A
1.6V
TO
OUTPUT
PIN
50pF
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD7891YPZ-1REEL | 功能描述:IC DAS 12BIT 8CH 44-PLCC RoHS:是 类别:集成电路 (IC) >> 数据采集 - ADCs/DAC - 专用型 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:50 系列:- 类型:数据采集系统（DAS） 分辨率（位）:16 b 采样率（每秒）:21.94k 数据接口:MICROWIRE?，QSPI?，串行，SPI? 电压电源:模拟和数字 电源电压:1.8 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:40-WFQFN 裸露焊盘 供应商设备封装:40-TQFN-EP（6x6） 包装:托盘 |
| AD7891YS1 | 制造商:AD 功能描述:New |
| AD7891YS-1 | 制造商:Analog Devices 功能描述:ADC Single 454.5ksps 12-bit Parallel/Serial 44-Pin MQFP |
| AD7891YS-1REEL | 制造商:Analog Devices 功能描述:ADC Single 454.5ksps 12-bit Parallel/Serial 44-Pin MQFP T/R 制造商:Analog Devices 功能描述:ADC SGL 454.5KSPS 12-BIT PARALLEL/SERL 44MQFP - Tape and Reel |
| AD7891YS-2 | 制造商:Analog Devices 功能描述:ADC Single 500ksps 12-bit Parallel/Serial 44-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:8 CHANNEL, 12-BIT ADC I.C. - Bulk |
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