参数资料
| 型号： | AD7891YPZ-1 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 19/20页 |
| 文件大小： | 0K |
| 描述： | IC DAS 12BIT 8CH 44-PLCC |
| 标准包装： | 1 |
| 类型： | 数据采集系统（DAS） |
| 分辨率（位）： | 12 b |
| 采样率（每秒）： | 500k |
| 数据接口： | 串行，并联 |
| 电压电源： | 单电源 |
| 电源电压： | 5V |
| 工作温度： | -55°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-LCC（J 形引线） |
| 供应商设备封装： | 44-PLCC（16.59x16.59） |
| 包装： | 管件 |
AD7891
–8–
REV. D
SERIAL INTERFACE MODE FUNCTIONS
When the part is configured for serial mode (MODE = 0), five of the 12 data input/output lines provide serial interface functions.
These functions are outlined below.
PLCC Pin No.
MQFP Pin No. Mnemonic
Description
18
12
SCLK
Serial Clock Input. This is an externally applied serial clock that is used to
load serial data to the control register and to access data from the
output register.
15
9
TFS
Transmit Frame Synchronization Pulse. Active low logic input with serial
data expected after the falling edge of this signal.
16
10
RFS
Receive Frame Synchronization Pulse. This is an active low logic input
with
RFS provided externally as a strobe or framing pulse to access serial data
from the output register. For applications that require that data be transmitted
and received at the same time,
RFS and TFS should be connected together.
21
15
DATA OUT
Serial Data Output. Sixteen bits of serial data are provided with the
data FORMAT bit and the three address bits of the control register
preceding the 12 bits of conversion data. Serial data is valid on the falling
edge of SCLK for 16 edges after
RFS goes low. Output conversion data
coding is twos complement when the FORMAT bit of the control register is
1 and straight binary when the FORMAT bit of the control register is 0.
17
11
DATA IN
Serial Data Input. Serial data to be loaded to the control register is provided
at this input. The first six bits of serial data are loaded to the control
register on the first six falling edges of SCLK after
TFS goes low. Serial
data on subsequent SCLK edges is ignored while
TFS remains low.
13, 14
7, 8
TEST
Test Pin. When the device is configured for serial mode of operation,
two of the pins which had been data inputs become test inputs. To ensure
correct operation of the device, both TEST inputs should be tied to a
logic low potential.
CONTROL REGISTER
The control register for the AD7891 contains six bits of information as described below. These six bits can be written to the control
register either in a parallel mode write operation or via a serial mode write operation. The default (power-on) condition of all bits in
the control register is 0. Six serial clock pulses must be provided to the part in order to write data to the control register. If
TFS
returns high before six serial clock cycles, no data transfer takes place to the control register and the write cycle has to be restarted to
write data to the control register. However, if the SWCONV bit of the register was previously set to a Logic 1 and
TFS is brought
high before six serial clock cycles, another conversion is initiated.
A2
Address Input. This input is the most significant address input for multiplexer channel selection.
A1
Address Input. This is the second most significant address input for multiplexer channel selection.
A0
Address Input. Least significant address input for multiplexer channel selection. When the address is written to
the control register, an internal pulse is initiated to allow for the multiplexer settling time and track/hold acquisi-
tion time before the track/hold goes into hold and conversion is initiated. When the internal pulse times out, the
track/hold goes into hold and conversion is initiated. The selected channel is given by the formula
AA
A
24
1
2
0
1
+
SWCONV
Conversion Start. Writing a 1 to this bit initiates a conversion in a similar manner to the
CONVST input. Con-
tinuous conversion starts do not take place when there is a 1 in this location. The internal pulse and the conver-
sion process are initiated when a 1 is written to this bit. With a 1 in this bit, the hardware conversion start, i.e.,
the
CONVST input, is disabled. Writing a 0 to this bit enables the hardware CONVST input.
SWSTBY
Standby Mode Input. Writing a 1 to this bit places the device in its standby or power-down mode. Writing a 0 to
this bit places the device in its normal operating mode.
FORMAT
Data Format. Writing a 0 to this bit sets the conversion data output format to straight (natural) binary. This
data format is generally used for unipolar input ranges. Writing a 1 to this bit sets the conversion data output
format to twos complement. This output data format is generally used for bipolar input ranges.
)
0
B
D
(
B
S
L
2
A1
A0
AV
N
O
C
W
SY
B
T
S
W
ST
A
M
R
O
F
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD7891YPZ-1REEL | 功能描述:IC DAS 12BIT 8CH 44-PLCC RoHS:是 类别:集成电路 (IC) >> 数据采集 - ADCs/DAC - 专用型 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:50 系列:- 类型:数据采集系统（DAS） 分辨率（位）:16 b 采样率（每秒）:21.94k 数据接口:MICROWIRE?，QSPI?，串行，SPI? 电压电源:模拟和数字 电源电压:1.8 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:40-WFQFN 裸露焊盘 供应商设备封装:40-TQFN-EP（6x6） 包装:托盘 |
| AD7891YS1 | 制造商:AD 功能描述:New |
| AD7891YS-1 | 制造商:Analog Devices 功能描述:ADC Single 454.5ksps 12-bit Parallel/Serial 44-Pin MQFP |
| AD7891YS-1REEL | 制造商:Analog Devices 功能描述:ADC Single 454.5ksps 12-bit Parallel/Serial 44-Pin MQFP T/R 制造商:Analog Devices 功能描述:ADC SGL 454.5KSPS 12-BIT PARALLEL/SERL 44MQFP - Tape and Reel |
| AD7891YS-2 | 制造商:Analog Devices 功能描述:ADC Single 500ksps 12-bit Parallel/Serial 44-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:8 CHANNEL, 12-BIT ADC I.C. - Bulk |
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