参数资料
型号: AD9523-1/PCBZ
厂商: Analog Devices Inc
文件页数: 35/60页
文件大小: 0K
描述: BOARD EVAL FOR AD9523-1
设计资源: AD9523(-1) Eval Board Schematic
AD9523(-1) BOM
AD9523(-1) Gerber Files
标准包装: 1
主要目的: 计时,时钟发生器
嵌入式:
已用 IC / 零件: AD9523
主要属性: 板载 PLL 环路滤波器
次要属性: LED 状态指示器
已供物品:
AD9523-1
Rev. B | Page 40 of 60
CONTROL REGISTERS
CONTROL REGISTER MAP
Register addresses that are not listed in Table 30 are not used, and writing to those registers has no effect. Registers that are marked as
reserved should never have their values changed. When writing to registers with bits that are marked reserved, the user should take care
to always write the default value for the reserved bits.
Table 30. Control Register Map
Addr
(Hex)
Register
Name
(MSB)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(LSB)
Bit 0
Default
Value
(Hex)
Serial Port Configuration
SPI mode
serial port
configuration
SDO
active
LSB first/
address
increment
Soft reset
Reserved
Soft reset
LSB first/
address
increment
SDO active
0x00
0x000
I2C mode
serial port
configuration
Reserved
Soft reset
Reserved
Soft reset
Reserved
0x00
0x004
Readback
control
Reserved
Read back
active registers
0x00
0x005
EEPROM customer version ID[7:0] (LSB)
0x00
0x006
EEPROM
customer
version ID
EEPROM customer version ID[15:8] (MSB)
0x00
Input PLL (PLL1)
0x010
10-bit REFA R divider[7:0] (LSB)
0x00
0x011
PLL1 REFA
R divider
control
Reserved
10-bit REFA R divider[9:8]
(MSB)
0x00
0x012
10-bit REFB R divider[7:0] (LSB)
0x00
0x013
PLL1 REFB
R divider
control
Reserved
10-bit REFB R divider[9:8]
(MSB)
0x00
0x014
PLL1 reference
test divider
Reserved
REF_TEST divider
0x00
0x015
PLL1 reserved
Reserved
0x00
0x016
10-bit PLL1 feedback divider[7:0] (LSB)
0x00
0x017
PLL1 feedback
N divider
control
Reserved
10-bit PLL1 feedback divider[9:8]
(MSB)
0x00
0x018
PLL1
charge
pump
tristate
PLL1 charge pump control
0x0C
0x019
PLL1 charge
pump control
Reserved
Enable SPI
control of
antibacklash
pulse width
Antibacklash
pulse width control
PLL1 charge pump mode
0x00
0x01A
PLL1
input receiver
control
REF_TEST
input
receiver
enable
REFB
differential
receiver
enable
REFA
differential
receiver
enable
REFB receiver
enable
REFA
receiver
enable
Input
REFA, REFB
receiver
power-
down
control
enable
OSC_IN
single-ended
receiver
mode enable
(CMOS mode)
OSC_IN
differential
receiver
mode enable
0x00
0x01B
REF_TEST,
REFA, REFB,
and ZD_IN
control
Bypass
REF_TEST
divider
Bypass
feedback
divider
Zero delay
mode
OSC_IN signal
feedback
for PLL1
ZD_IN
single-
ended
receiver
mode
enable
(CMOS
mode)
ZD_IN
differ-
ential
receiver
mode
enable
REFB
single-ended
receiver
mode enable
(CMOS mode)
REFA
single-ended
receiver
mode enable
(CMOS mode)
0x00
0x01C
PLL1
miscellaneous
control
Enable
REFB
R divider
indepen-
dent
division
control
OSC_CTRL
control
voltage to
VCC/2
when ref
clock fai
ls
Reserved
Reference selection mode
Bypass REFB
R divider
Bypass REFA
R divider
0x00
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