参数资料
型号: AD9540BCPZ-REEL7
厂商: Analog Devices Inc
文件页数: 10/32页
文件大小: 0K
描述: IC CLOCK GEN/SYNTHESIZER 48LFCSP
标准包装: 750
类型: 时钟发生器
PLL:
输入: 时钟
输出: CML,PECL
电路数: 1
比率 - 输入:输出: 2:2
差分 - 输入:输出: 是/是
频率 - 最大: 655MHz
除法器/乘法器: 是/无
电源电压: 1.71 V ~ 1.89 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-VFQFN 裸露焊盘,CSP
供应商设备封装: 48-LFCSP-VQ(7x7)
包装: 带卷 (TR)
AD9540
Rev. A | Page 18 of 32
04947-046
REFIN
CLK2
CP_OUT
DDS
÷R
VCO
AD9540
LPF
DAC
÷N
CML
DRIVER
2.5GHz
TONE
8-LEVEL FSK
(FC = 100MHz)
BPF
25MHz
CRYSTAL
Figure 36. ISM Band Modulator (LO & Baseband Generation)
APPLICATION CIRCUIT DESCRIPTIONS
Dual Clock Configuration
In this loop, M = 1, N = 16, and R = 4. The DDS (direct digital
synthesizer) tuning word is also equal to , so that the
frequency of CLOCK1’ equals the frequency of CLOCK 1.
Phase adjustments in the DDS provide 14-bit programmable
rising edge delay capability of CLOCK1’ with respect to
CLOCK1 (see Figure 32).
Optical Networking Clock
This is the AD9540 configured as an optical networking clock.
The loop can be used to generate a 622 MHz clock for OC12.
The DDS can be programmed to output 8 kHz to serve as a base
reference for other circuits in the subsystem (see Figure 33).
Fractional-Divider Loop
This loop offers the precise frequency
division (48-bit) of the DDS in the feedback path as well as the
frequency sweeping capability of the DDS. Programming the
DDS to sweep from 24 MHz to 25 MHz sweeps the output of
the VCO from 2.7 GHz to 2.6 GHz. The reference in this case is
a simple crystal (see Figure 34).
Direct Upconversion
The AD9540 is configured to use the DDS as a precision
reference to the PLL. Since the VCO is <655 MHz, it can be fed
straight into the phase frequency detector feedback.
LO and Baseband Modulation Generation
Using the AD9540 PLL section to generate LO and the DDS
portion to generate a modulated baseband, this circuit uses an
external mixer to perform some simple modulation at RF ISM
band frequencies (see Figure 36).
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