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参数资料
| 型号： | AD9540BCPZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 11/32页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN/SYNTHESIZER 48LFCSP |
| 标准包装： | 750 |
| 类型： | 时钟发生器 |
| PLL： | 是 |
| 输入： | 时钟 |
| 输出： | CML，PECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 655MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 1.71 V ~ 1.89 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP-VQ（7x7） |
| 包装： | 带卷 (TR) |
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AD9540
Rev. A | Page 19 of 32
THEORY OF OPERATION
PLL CIRCUITRY
The AD9540 includes an RF divider (divide-by-R), a 48-bit
DDS core, a 14-bit programmable delay adjustment, a 10-bit
DAC (digital-to-analog converter), a phase frequency detector,
and a programmable output current charge pump. Incorporat-
ing these blocks together, users can generate many useful
circuits for clock synthesis. A few simple examples are shown in
the Typical Performance Characteristics section.
The RF divider accepts differential or single-ended signals up to
2.7 GHz on the CLK1 input pin. The RF divider also supplies
the SYSCLK input to the DDS. Because the DDS operates only
up to 400 MSPS, device function requires that for any CLK1
signal >400 MHz, the RF divider must be engaged. The RF
divider can be programmed to take values of 1, 2, 4, or 8. The
ratio for the divider is programmed in the control register. The
output of the divider can be routed to the input of the on-chip
CML driver. For lower frequency input signals, it is possible to
use the divider to divide the input signal to the CML driver and
to use the undivided input of the divider as the SYSCLK input
to the DDS, or vice versa. In all cases, the SYSCLK to the DDS
should not exceed 400 MSPS.
The on-chip phase frequency detector has two differential
inputs, REFIN (the reference input) and CLK2 (the feedback or
oscillator input). These differential inputs can be driven by
single-ended signals. When doing so, tie the unused input
through a 100 pF capacitor to the analog supply (AVDD). The
maximum speed of the phase frequency detector inputs is
200 MHz. Each of the inputs has a buffer and a divider (÷M on
REFIN and ÷N on CLK2) that operates up to 655 MHz. If the
signal exceeds 200 MHz, the divider must be used. The dividers
are programmed through the control registers and take any
integer value between 1 and 16.
The REFIN input also has the option of engaging an in-line
oscillator circuit. Engaging this circuit means that the REFIN
input can be driven with a crystal in the range of 20 MHz ≤
REFIN ≤ 30 MHz.
The charge pump outputs a current in response to an error
signal generated in the phase frequency detector. The output
current is programmed through by placing a resistor (CP_RSET)
from the CP_RSET pin to ground. The value is dictated by
SET
CP_R
CP_IOUT
1.55
=
This sets the charge pump reference output current. Also, a
programmable scaler multiplies this base value by any integer
from 1 to 8, programmable through the CP current scale bits in
the Control Function Register 2, CFR2[2:0].
CML DRIVER
An on-chip current mode logic (CML) driver is also included.
This CML driver generates very low jitter clock edges. The
outputs of the CML driver are current outputs that drive PECL
levels when terminated into a 100 load. The continuous
output current of the driver is programmed by attaching a
resistor from the DRV_RSET pin to ground (nominally 4.02 k
for a continuous current of 7.2 mA). An optional on-chip
current programming resistor is enabled by setting a bit in the
control register. The rising edge and falling edge slew rates are
independently programmable to help control overshoot and
ringing by the application of surge current during rising edge
and falling edge transitions (see Figure 37). There is a default
surge current of 7.6 mA on the rising edge and of 4.05 mA on
the falling edge. Bits in the control register enable additional
rising edge and falling edge surge current, as well as disable the
default surge current (see the Control Register Bit Descriptions
section for details). The CML driver can be driven by:
RF divider input (CLK1 directly to the CML driver)
RF divider output
CLK2 input
04947-017
I(t)
t
~250ps
RISING EDGE SURGE
CONTINUOUS
FALLING EDGE SURGE
Figure 37. Rising Edge and Falling Edge Surge Current Out of the
CML Clock Driver, as Opposed to the Steady State Continuous Current
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9540PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:655 MHz Low Jitter Clock Generator |
| AD9540-VCO/PCB | 制造商:Analog Devices 功能描述:EVAL BD FOR AD9540 ,655 MHZ LOW JITTER CLOCK GEN - Trays |
| AD9540-VCO/PCBZ | 功能描述:BOARD EVAL CLK GEN SYNTH 48LFCSP RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:- 主要目的:电信，线路接口单元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要属性:T1/J1/E1 LIU 次要属性:- 已供物品:板，电源，线缆，CD 其它名称:82EBV2081 |
| AD9542/PCBZ | |
| AD9542BCPZ | 功能描述:SYNCHRONIZER & ADAPTIVE CLOCK TR 制造商:analog devices inc. 系列:* 包装:托盘 零件状态:在售 安装类型:表面贴装 封装/外壳:64-WFQFN 裸露焊盘 供应商器件封装:64-LFCSP（9x9） 标准包装:1 |
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