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参数资料
| 型号： | AD9540BCPZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 14/32页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN/SYNTHESIZER 48LFCSP |
| 标准包装： | 750 |
| 类型： | 时钟发生器 |
| PLL： | 是 |
| 输入： | 时钟 |
| 输出： | CML，PECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 655MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 1.71 V ~ 1.89 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP-VQ（7x7） |
| 包装： | 带卷 (TR) |
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AD9540
Rev. A | Page 21 of 32
MODES OF OPERATION
SELECTABLE CLOCK FREQUENCIES AND
SELECTABLE EDGE DELAY
Because the precision driver is implemented using a DDS, it
is possible to store multiple clock frequency words to enable
externally switchable clock frequencies. The phase accumulator
runs at a fixed frequency, according to the active profile clock
frequency word. Likewise, any delay applied to the rising and
falling edges is a static value that comes from the delay shift
word of the active profile. The device has eight different
phase/frequency profiles, each with its own 48-bit clock
frequency word and 14-bit delay shift word. Profiles are selected
by applying their digital values on the clock select pins (Pin S0,
Pin S1, and Pin S2). It is not possible to use the phase offset of
one profile and the frequency tuning word of another.
SYNCHRONIZATION MODES FOR MULTIPLE DEVICES
In a DDS system, the SYNC_CLK is derived internally from the
master system clock, SYSCLK, with a ÷4 divider. Because the
divider does not power up to a known state, multiple devices in a
system might have staggered clock phase relationships, because
each device can potentially generate the SYNC_CLK rising edge
from any one of four rising edges of SYSCLK. This ambiguity can
be resolved by employing digital synchronization logic to control
the phase relationships of the derived clocks among different
devices in the system. Note that the synchronization functions
included on the AD9540 control only the timing relationships
among different digital clocks. They do not compensate for the
analog timing delay on the system clock due to mismatched phase
relationships on the input clock, CLK1 (see Figure 38).
SYSCLK DUT1
SYNC_CLK
DUT1
SYNC_CLK DUT2 w/o
SYNC_CLK ALIGNED
SYSCLK DUT2
SYNC_CLK DUT2 w/
SYNC_CLK ALIGNED
01
2
30
01
2
3
SYNCHRONIZATION FUNCTIONS CAN ALIGN
DIGITAL CLOCK RELATIONSHIPS, THEY
CANNOT DESKEW THE EDGES OF CLOCKS
04947-018
Figure 38. Synchronization Functions: Capabilities and Limitations
Automatic Synchronization
In automatic synchronization mode, the device is placed in slave
mode and automatically aligns the internal SYNC_CLK to a master
SYNC_CLK signal, supplied on the SYNC_IN input. When this bit
is enabled, the STATUS is not available as an output; however, an
out-of-lock condition can be detected by reading Control Function
Register 1 and checking the status of the STATUS_Error bit. The
automatic synchronization function is enabled by setting the
Control Function Register 1, Automatic Synchronization Bit
CFR1[3]. To employ this function at higher clock rates
(SYNC_CLK > 62.5 MHz, SYSCLK > 250 MHz), the high speed
sync enable bit (CFR1[0]) should be set as well.
Manual Synchronization, Hardware Controlled
In this mode, the user controls the timing relationship of the
SYNC_CLK with respect to SYSCLK. When hardware manual
synchronization is enabled, the SYNC_IN/STATUS pin
becomes a digital input. For each rising edge detected on the
SYNC_IN input, the device advances the SYNC_IN rising edge
by one SYSCLK period. When this bit is enabled, the STATUS is
not available as an output; however, an out-of-lock condition
can be detected by reading Control Function Register 1 and
checking the status of the STATUS_Error bit. This synchro-
nization function is enabled by setting the Hardware Manual
Synchronization Enable Bit CFR1[1].
Manual Synchronization, Software Controlled
In this mode, the user controls the timing relationship between
SYNC_CLK and SYSCLK through software programming.
When the software manual synchronization bit (CFR1[2]) is set
high, the SYNC_CLK is advanced by one SYSCLK cycle. Once
this operation is complete, the bit is cleared. The user can set
this bit repeatedly to advance the SYNC_CLK rising edge
multiple times. Because the operation does not use the
SYNC_IN/STATUS pin as a SYNC_IN input, the STATUS
signal can be monitored on the STATUS pin during this
operation.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9540PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:655 MHz Low Jitter Clock Generator |
| AD9540-VCO/PCB | 制造商:Analog Devices 功能描述:EVAL BD FOR AD9540 ,655 MHZ LOW JITTER CLOCK GEN - Trays |
| AD9540-VCO/PCBZ | 功能描述:BOARD EVAL CLK GEN SYNTH 48LFCSP RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:- 主要目的:电信，线路接口单元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要属性:T1/J1/E1 LIU 次要属性:- 已供物品:板，电源，线缆，CD 其它名称:82EBV2081 |
| AD9542/PCBZ | |
| AD9542BCPZ | 功能描述:SYNCHRONIZER & ADAPTIVE CLOCK TR 制造商:analog devices inc. 系列:* 包装:托盘 零件状态:在售 安装类型:表面贴装 封装/外壳:64-WFQFN 裸露焊盘 供应商器件封装:64-LFCSP（9x9） 标准包装:1 |
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