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参数资料
| 型号： | AD9553/PCBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 17/44页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9553 |
| 设计资源： | AD9553 Eval Brd BOM AD9553 Eval Brd Schematic |
| 标准包装： | 1 |
| 主要目的： | 计时，时钟缓冲器 / 驱动器 / 接收器 / 变换器 |
| 已用 IC / 零件： | AD9553 |
| 已供物品： | 板 |
| 相关产品： | AD9553BCPZ-ND - IC INTEGER-N CLCK GEN 32LFCSP AD9553BCPZ-REEL7-ND - IC INTEGER-N CLCK GEN 32LFCSP |
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AD9553
Rev. A | Page 24 of 44
The mode control bits establish the logic family and output pin
function of the associated output driver per Table 19. The logic
families include LVDS, LVPECL, and CMOS. Because both
output drivers support the LVDS and LVPECL logic families,
each driver has two pins to handle the differential signals associated
with these two logic families. The OUT1 driver uses the OUT1
and OUT1 pins and the OUT2 driver uses the OUT2 and OUT2
pins. However, the CMOS logic family handles only single-ended
signals, thereby requiring only one pin. Even though CMOS
only requires one pin, both pins of OUT1 and both pins of
OUT2 have a dedicated CMOS driver.
Note that the LVPECL mode of the AD9553 is not implemented
using an emitter-follower topology, and therefore, a pull-down
resistor is not needed (and should be avoided) on the output pins.
Rather, it uses a CMOS output driver whose output amplitude
and common-mode voltage are compatible with LVPECL speci-
fications. 100 termination across the output pair is still
recommended.
The user has the option to disable (that is, tristate) either or both of
the pins for OUT1 and/or OUT2 via the mode control bits (see
Table 19 for the 001, 010, and 011 bit patterns). Alternatively,
the user can make both pins active (see Table 19, Bit Pattern 000)
to produce two single-ended CMOS output clocks at OUT1
and/or OUT2.
Table 19. Output Mode Control Bits
Mode Control Bits
Logic Family
Pin Function of the
Output Driver
000
CMOS
Both pins active
001
CMOS
Positive pin active,
negative pin tristate
010
CMOS
Positive pin tristate,
negative pin active
011
CMOS
Both pins tristate
100
LVDS
Both pins active
101
LVPECL
Both pins active
110
Unused
111
Unused
Note that the pin decoder for the OM2 to OM0 pins generates
two sets of mode control bits: one set for the OUT1 driver and
another set for the OUT2 driver. The relationship between the
logic levels applied to the OM2 to OM0 pins and the resulting
mode control bits appears in Table 20.
Table 20. OM2 to OM0 Pin Decoder
Pin OM2 to
Pin OM0
Mode Control Bits
OUT1
OUT2
000
101
001
101
100
010
100
101
011
101
001
100
101
100
001
110
001
100
111
001
This decoding scheme allows the OM2 to OM0 pins to establish a
matrix of logic family selections for the OUT1 and OUT2 drivers as
shown in Table 21. Note that when the OM2 to OM0 pins select the
CMOS logic family, the signal at the OUT1 pin is a phase aligned
replica of the signal at the OUT1 pin and the signal at the OUT2
pin is a phase aligned replica of the signal at the OUT2 pin.
Table 21. Logic Family Assignment via the OM2 to OM0 Pins
Pin OM2 to
Pin OM0
Logic Family
OUT1
OUT2
000
LVPECL
001
LVPECL
LVDS
010
LVDS
LVPECL
011
LVPECL
CMOS
100
LVDS
101
LVDS
CMOS
110
CMOS
LVDS
111
CMOS
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9554/PCBZ | 功能描述:AD9554 - Timing, Clock Generator Evaluation Board 制造商:analog devices inc. 系列:- 零件状态:有效 主要用途:计时，时钟发生器 嵌入式:- 使用的 IC/零件:AD9554 主要属性:- 辅助属性:LED 状态指示器 所含物品:板 标准包装:1 |
| AD9554-1/PCBZ | 功能描述:AD9554-1 - Timing, Clock Generator Evaluation Board 制造商:analog devices inc. 系列:- 零件状态:有效 主要用途:计时，时钟发生器 嵌入式:- 使用的 IC/零件:AD9554-1 主要属性:- 辅助属性:LED 状态指示器 所含物品:板 标准包装:1 |
| AD9554-1BCPZ | 功能描述:IC PLL CLOCK GEN 4OUT 72LFCSP 制造商:analog devices inc. 系列:- 包装:托盘 零件状态:有效 PLL:是 主要用途:以太网，SONET/SDH，Stratum 输入:CMOS，LVDS 输出:HCSL，LVDS，LVPECL 电路数:1 比率 - 输入:输出:4：4 差分 - 输入:输出:是/是 频率 - 最大值:942MHz 电压 - 电源:1.4 V ~ 2.625 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:56-WFQFN 裸焊盘，CSP 供应商器件封装:56-LFCSP-WQ（8x8） 标准包装:1 |
| AD9554-1BCPZ-REEL7 | 功能描述:IC PLL CLOCK GEN 4OUT 72LFCSP 制造商:analog devices inc. 系列:- 包装:带卷（TR） 零件状态:有效 PLL:是 主要用途:以太网，SONET/SDH，Stratum 输入:CMOS，LVDS 输出:HCSL，LVDS，LVPECL 电路数:1 比率 - 输入:输出:4：4 差分 - 输入:输出:是/是 频率 - 最大值:942MHz 电压 - 电源:1.4 V ~ 2.625 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:56-WFQFN 裸焊盘，CSP 供应商器件封装:56-LFCSP-WQ（8x8） 标准包装:750 |
| AD9554BCPZ | 功能描述:IC CLOCK TRANSLATOR 8OUT 72LFCSP 制造商:analog devices inc. 系列:- 包装:托盘 零件状态:有效 PLL:是 主要用途:以太网，SONET/SDH，Stratum 输入:CMOS，LVDS 输出:HCSL，LVDS，LVPECL 电路数:1 比率 - 输入:输出:4：8 差分 - 输入:输出:是/是 频率 - 最大值:941MHz 电压 - 电源:1.47 V ~ 1.89 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:72-VFQFN 裸露焊盘，CSP 供应商器件封装:72-LFCSP-VQ（10x10） 标准包装:1 |
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