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| 型号： | AD9553BCPZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/44页 |
| 文件大小： | 0K |
| 描述： | IC INTEGER-N CLCK GEN 32LFCSP |
| 标准包装： | 1,500 |
| 类型： | 时钟/频率转换器 |
| PLL： | 是 |
| 主要目的： | 以太网，GPON，SONET/SHD，T1/E1 |
| 输入： | CMOS，LVDS，晶体 |
| 输出： | CMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 810MHz |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP（5x5） |
| 包装： | 带卷 (TR) |
| 配用： | AD9553/PCBZ-ND - BOARD EVAL FOR AD9553 |
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AD9553
Rev. A | Page 20 of 44
A[3:0]
4
SPI/OM[2:0]
3
0
1
0
3
0
1
FUNCTION
ABC BITS
0
1
FUNCTION
XYZ BITS
ENABLE SPI CONTROL
OF OUTPUT MODE
ENABLE SPI CONTROL
OF OUTPUT ABC BITS
ENABLE SPI CONTROL
OF FUNCTIONING XYZ
OUTPUT
MODE
CONTROL
FUNCTION
BITS
REGISTER MAP
FUNCTION
MUXES
SPI CONTROLLER
FREQUENCY
SELECTION
PINS DECODER
OUTPUT
MODE
CONTROL
DECODER
OUTPUT MODE
CONTROL
FUNCTION
ABC
FUNCTION
XYZ
Y[5:0]
6
3
SPI MODE
08565-
100
Figure 28. Control Mode Diagram
Although the SPI and pin control modes are functionally
independent, it is possible to mix the control modes. For
example, suppose that pin control satisfies all of the require-
ments for an application except for the value of the P2 divider
(which is associated with OUT2). The user could do the
following:
Activate SPI mode via the frequency selection pins.
Program the desired P0, P1, and P2 values in the register
map (Register 0x15 to Register 0x18).
Set the enable SPI control bit for the output dividers
(Register 0x14[2] = 1).
Calibrate the VCO by enabling SPI control of VCO
calibration (Register 0x0E[2] = 1), then issue a calibrate
command (Register 0x0E[7] = 1). Be sure to program the
N divider, R dividers, ÷5 dividers, and ×2 multipliers to the
values defined by the Ax and Yx pin settings prior to cali-
brating the VCO.
Restore the original settings to the frequency selection pins
to invoke the desired frequency selection.
In this way, the function muxes that control P0, P1, and P2 select
the appropriate register bits as the source for controlling the
dividers, while all the other function muxes select the pin decoders
as the source for controlling the other functions. Note that the
dividers remain under register control until the user activates
SPI mode and writes Register 0x14[2] = 0, thereby causing the
function mux to use the frequency selection pins decoder as the
source for controlling the dividers, instead of the register map.
DESCRIPTION OF FUNCTIONAL BLOCKS
Reference Inputs
The default configuration of the AD9553 provides up to two
single-ended input clock receivers, REFA and REFB, which are
high impedance CMOS inputs. In applications that require redun-
dant reference clocks with switchover capability, REFA is the
primary reference and REFB the secondary reference. Alternatively,
the user can configure the input (via the serial I/O port) as a
single differential receiver. In this case, the REFB input func-
tions as REFA (the complementary input of REFA). Note that
in this configuration the device operates with only one reference
input clock, eliminating the need for switchover functionality.
XTAL Input
The AD9553 accepts an optional 25 MHz crystal resonator
connected across the XTAL pins. Alternatively, it accepts a
single-ended clock source (CMOS compatible) connected to
either one of the XTAL input pins (in this case, the unused
input remains floating). Unless otherwise programmed, the
device expects the crystal to have a specified load capacitance
of 10 pF (default). The AD9553 provides the necessary load
capacitance internally. The internal load capacitance consists
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9554/PCBZ | 功能描述:AD9554 - Timing, Clock Generator Evaluation Board 制造商:analog devices inc. 系列:- 零件状态:有效 主要用途:计时，时钟发生器 嵌入式:- 使用的 IC/零件:AD9554 主要属性:- 辅助属性:LED 状态指示器 所含物品:板 标准包装:1 |
| AD9554-1/PCBZ | 功能描述:AD9554-1 - Timing, Clock Generator Evaluation Board 制造商:analog devices inc. 系列:- 零件状态:有效 主要用途:计时，时钟发生器 嵌入式:- 使用的 IC/零件:AD9554-1 主要属性:- 辅助属性:LED 状态指示器 所含物品:板 标准包装:1 |
| AD9554-1BCPZ | 功能描述:IC PLL CLOCK GEN 4OUT 72LFCSP 制造商:analog devices inc. 系列:- 包装:托盘 零件状态:有效 PLL:是 主要用途:以太网，SONET/SDH，Stratum 输入:CMOS，LVDS 输出:HCSL，LVDS，LVPECL 电路数:1 比率 - 输入:输出:4：4 差分 - 输入:输出:是/是 频率 - 最大值:942MHz 电压 - 电源:1.4 V ~ 2.625 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:56-WFQFN 裸焊盘，CSP 供应商器件封装:56-LFCSP-WQ（8x8） 标准包装:1 |
| AD9554-1BCPZ-REEL7 | 功能描述:IC PLL CLOCK GEN 4OUT 72LFCSP 制造商:analog devices inc. 系列:- 包装:带卷（TR） 零件状态:有效 PLL:是 主要用途:以太网，SONET/SDH，Stratum 输入:CMOS，LVDS 输出:HCSL，LVDS，LVPECL 电路数:1 比率 - 输入:输出:4：4 差分 - 输入:输出:是/是 频率 - 最大值:942MHz 电压 - 电源:1.4 V ~ 2.625 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:56-WFQFN 裸焊盘，CSP 供应商器件封装:56-LFCSP-WQ（8x8） 标准包装:750 |
| AD9554BCPZ | 功能描述:IC CLOCK TRANSLATOR 8OUT 72LFCSP 制造商:analog devices inc. 系列:- 包装:托盘 零件状态:有效 PLL:是 主要用途:以太网，SONET/SDH，Stratum 输入:CMOS，LVDS 输出:HCSL，LVDS，LVPECL 电路数:1 比率 - 输入:输出:4：8 差分 - 输入:输出:是/是 频率 - 最大值:941MHz 电压 - 电源:1.47 V ~ 1.89 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:72-VFQFN 裸露焊盘，CSP 供应商器件封装:72-LFCSP-VQ（10x10） 标准包装:1 |
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