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参数资料
| 型号： | AD9553BCPZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 24/44页 |
| 文件大小： | 0K |
| 描述： | IC INTEGER-N CLCK GEN 32LFCSP |
| 标准包装： | 1,500 |
| 类型： | 时钟/频率转换器 |
| PLL： | 是 |
| 主要目的： | 以太网，GPON，SONET/SHD，T1/E1 |
| 输入： | CMOS，LVDS，晶体 |
| 输出： | CMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 810MHz |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP（5x5） |
| 包装： | 带卷 (TR) |
| 配用： | AD9553/PCBZ-ND - BOARD EVAL FOR AD9553 |
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AD9553
Rev. A | Page 30 of 44
SERIAL CONTROL PORT
The AD9553 serial control port is a flexible, synchronous, serial
communications port that allows an easy interface to many
industry-standard microcontrollers and microprocessors. Single
or multiple byte transfers are supported, as well as MSB first or
LSB first transfer formats. The AD9553 serial control port is
configured for a single bidirectional I/O pin (SDIO only). The
serial control port uses 16-bit instructions, which allow access
to the entire register address range (0x00 to 0x34).
The serial control port has two types of registers: read-only and
buffered. Read-only registers are nonbuffered and ignore write
commands. All writable registers are buffered (also referred to
as mirrored) and require an I/O update to transfer the new values
from a temporary buffer on the chip to the actual register. To
invoke an I/O update, write a 1 to the I/O update bit found in
Register 0x05[0]. Because any number of bytes of data can be
changed before issuing an update command, the update simul-
taneously enables all register changes occurring since any
previous update.
SERIAL CONTROL PORT PIN DESCRIPTIONS
The serial data clock (SCLK) is the serial shift clock. This pin is
an input. SCLK is used to synchronize serial control port reads
and writes. Write data bits are registered on the rising edge of
this clock, and read data bits are registered on the falling edge.
The digital serial data input/output (SDIO) pin is a dual-purpose
pin that acts as input only or as an input/output. The AD9553
defaults to bidirectional pins for I/O.
The chip select bar (CS) is an active low control that gates the read
and write cycles. When CS is high, SDIO is in a high impedance
state. See the Operation of the Serial Control Port section on the
use of the CS pin in a communication cycle.
AD9553
SERIAL
CONTROL
PORT
13
14
12
OM1/SCLK
OM0/SDIO
OM2/CS
08565-
006
Figure 34. Serial Control Port
OPERATION OF THE SERIAL CONTROL PORT
Framing a Communication Cycle with CS
The CS line gates the communication cycle (a write or a read oper-
ation). CS must be brought low to initiate a communication cycle.
The CS stall high function is supported in modes where three
or fewer bytes of data (plus instruction data) are transferred.
Bits[W1:W0] must be set to 00, 01, or 10 (see Table 24). In these
modes, CS may temporarily return high on any byte boundary,
allowing time for the system controller to process the next byte.
CS can go high on byte boundaries only and can go high during
either part (instruction or data) of the transfer. During this period,
the serial control port state machine enters a wait state until all
data has been sent. If the system controller decides to abort before
the complete transfer of all the data, the state machine must be reset
either by completing the remaining transfer or by returning the
CS line low for at least one complete SCLK cycle (but fewer than
eight SCLK cycles). A rising edge on the CS pin on a nonbyte
boundary terminates the serial transfer and flushes the buffer.
Table 24. Byte Transfer Count
Bit W1
Bit W0
Bytes to Transfer
(Excluding the 2-Byte Instruction)
0
1
0
1
2
1
0
3
1
Streaming mode
In the streaming mode (Bits[W1:W0] = 11), any number of data
bytes can be transferred in a continuous stream. The register
address is automatically incremented or decremented (see the
MSB/LSB First Transfers section). CS must be raised at the end
of the last byte to be transferred, thereby ending the stream mode.
Communication Cycle—Instruction Plus Data
There are two parts to a communication cycle with the AD9553.
The first part writes a 16-bit instruction word into the AD9553,
coincident with the first 16 SCLK rising edges. The instruction
word provides the AD9553 serial control port with information
regarding the data transfer, which is the second part of the commu-
nication cycle. The instruction word defines whether the upcoming
data transfer is a read or a write, the number of bytes in the data
transfer, and the starting register address for the first byte of the
data transfer.
Write
If the instruction word is for a write operation (Bit I15 = 0), the
second part is the transfer of data into the serial control port
buffer of the AD9553. The length of the transfer (1, 2, or 3 bytes;
or streaming mode) is indicated by two bits (Bits[W1:W0]) in
the instruction byte. The length of the transfer indicated by
(Bits[W1:W0]) does not include the two-byte instruction. CS
can be raised after each sequence of eight bits to stall the bus
(except after the last byte, where it ends the cycle). When the bus is
stalled, the serial transfer resumes when CS is lowered. Stalling on
nonbyte boundaries resets the serial control port.
Read
If the instruction word is for a read operation (Bit I15 = 1), the
next N × 8 SCLK cycles clock out the data from the address
specified in the instruction word, where N is 1, 2, 3, or 4, as
determined by Bits[W1:W0]. In this case, 4 is used for streaming
mode, where four or more words are transferred per read. The
data readback is valid on the falling edge of SCLK.
The default mode of the AD9553 serial control port is bidirec-
tional mode, and the data readback appears on the SDIO pin.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9554/PCBZ | 功能描述:AD9554 - Timing, Clock Generator Evaluation Board 制造商:analog devices inc. 系列:- 零件状态:有效 主要用途:计时，时钟发生器 嵌入式:- 使用的 IC/零件:AD9554 主要属性:- 辅助属性:LED 状态指示器 所含物品:板 标准包装:1 |
| AD9554-1/PCBZ | 功能描述:AD9554-1 - Timing, Clock Generator Evaluation Board 制造商:analog devices inc. 系列:- 零件状态:有效 主要用途:计时，时钟发生器 嵌入式:- 使用的 IC/零件:AD9554-1 主要属性:- 辅助属性:LED 状态指示器 所含物品:板 标准包装:1 |
| AD9554-1BCPZ | 功能描述:IC PLL CLOCK GEN 4OUT 72LFCSP 制造商:analog devices inc. 系列:- 包装:托盘 零件状态:有效 PLL:是 主要用途:以太网，SONET/SDH，Stratum 输入:CMOS，LVDS 输出:HCSL，LVDS，LVPECL 电路数:1 比率 - 输入:输出:4：4 差分 - 输入:输出:是/是 频率 - 最大值:942MHz 电压 - 电源:1.4 V ~ 2.625 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:56-WFQFN 裸焊盘，CSP 供应商器件封装:56-LFCSP-WQ（8x8） 标准包装:1 |
| AD9554-1BCPZ-REEL7 | 功能描述:IC PLL CLOCK GEN 4OUT 72LFCSP 制造商:analog devices inc. 系列:- 包装:带卷（TR） 零件状态:有效 PLL:是 主要用途:以太网，SONET/SDH，Stratum 输入:CMOS，LVDS 输出:HCSL，LVDS，LVPECL 电路数:1 比率 - 输入:输出:4：4 差分 - 输入:输出:是/是 频率 - 最大值:942MHz 电压 - 电源:1.4 V ~ 2.625 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:56-WFQFN 裸焊盘，CSP 供应商器件封装:56-LFCSP-WQ（8x8） 标准包装:750 |
| AD9554BCPZ | 功能描述:IC CLOCK TRANSLATOR 8OUT 72LFCSP 制造商:analog devices inc. 系列:- 包装:托盘 零件状态:有效 PLL:是 主要用途:以太网，SONET/SDH，Stratum 输入:CMOS，LVDS 输出:HCSL，LVDS，LVPECL 电路数:1 比率 - 输入:输出:4：8 差分 - 输入:输出:是/是 频率 - 最大值:941MHz 电压 - 电源:1.47 V ~ 1.89 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:72-VFQFN 裸露焊盘，CSP 供应商器件封装:72-LFCSP-VQ（10x10） 标准包装:1 |
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