参数资料
| 型号： | AD9600ABCPZ-150 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 26/72页 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 150MSPS 64LFCSP |
| 标准包装： | 1 |
| 位数： | 10 |
| 采样率（每秒）： | 150M |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 890mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 托盘 |
| 输入数目和类型： | 4 个单端，单极；2 个差分，单极 |
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AD9600
Rev. B | Page 32 of 72
Increment Gain (IG) and Decrement Gain (DG)
The increment gain and decrement gain indicators are intended
to be used together to provide information to enable external gain
control. The decrement gain indicator works in conjunction with
the coarse upper threshold bits, asserting when the input
magnitude is greater than the 3-bit value in the coarse upper
threshold register (Address 0x105). The increment gain indicator,
similarly, corresponds with the fine lower threshold bits, except
that it is asserted only if the input magnitude is less than the
value programmed in the fine lower threshold register after the
dwell time elapses. This dwell time is set by the 16-bit increase
gain dwell time register (Address 0x10A and Address 0x10B) and
is in units of ADC input clock cycles ranging from 1 to 65,535. The
fine lower threshold register is a 13-bit register that is compared
with the magnitude at the output of the ADC. This comparison
is subject to the ADC clock latency but allows a finer, more
accurate comparison. The fine threshold magnitude is defined
in Equation 1 (see the Fine Upper Threshold (F_UT) section).
The decrement gain output is influenced by the fast detect output
pins, which provide a fast indication of potential overrange
conditions. Assertion of the increment gain indicator is based
on the comparison at the output of the ADC, requiring the input
magnitude to remain below an accurate, programmable level for a
predefined period before signaling external circuitry to increase
the gain.
The operation of the IG and DG indicators is shown in Figure 66.
0
69
09
-09
7
UPPER THRESHOLD (COARSE OR FINE)
FINE LOWER THRESHOLD
IG
DG
F_LT
C_UT OR F_UT*
DWELL TIME
TIMER RESET BY
RISE ABOVE F_LT
TIMER COMPLETES BEFORE
SIGNAL RISES ABOVE F_LT
NOTE: OUTPUTS FOLLOW THE INSTANTANEOUS SIGNAL LEVEL AND NOT THE ENVELOPE BUT ARE GUARANTEED ACTIVE FOR A MINIMUM OF TWO ADC CLOCK CYCLES.
*C_UT AND F_UT DIFFER ONLY IN ACCURACY AND LATENCY.
DWELL TIME
Figure 66. Threshold Settings for C_UT, F_UT, F_LT, IG, and DG
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9600BCPZ-105 | 制造商:Analog Devices 功能描述:ADC Dual Pipelined 105Msps 10-bit Parallel/LVDS 64-Pin LFCSP EP |
| AD9600BCPZ-125 | 制造商:Analog Devices 功能描述:ADC Dual Pipelined 125Msps 10-bit Parallel/LVDS 64-Pin LFCSP EP |
| AD9600BCPZ-150 | 制造商:Analog Devices 功能描述: |
| AD9601 | 制造商:AD 制造商全称:Analog Devices 功能描述:10-Bit, 200 MSPS/250 MSPS 1.8 V Analog-to-Digital Converter |
| AD9601-250EBZ | 功能描述:数据转换 IC 开发工具 10-Bit 250 Msps LowPwr CMOS ADC RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V |
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