参数资料
| 型号： | AD9774ASZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/24页 |
| 文件大小： | 0K |
| 描述： | IC DAC 14BIT 32MSPS 44MQFP |
| 产品变化通告： | Product Discontinuance 27/Oct/2011 |
| 标准包装： | 800 |
| 系列： | TxDAC+® |
| 设置时间： | 35ns |
| 位数： | 14 |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 电压电源： | 模拟和数字 |
| 功率耗散（最大）： | 1.13W |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-QFP |
| 供应商设备封装： | 44-MQFP（10x10） |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 2 电流，单极；2 电流，双极 |
| 采样率（每秒）： | 32M |
AD9774
–13–
REV. B
50pF
+1.2V REF
AVDD
REFLO
CURRENT
SOURCE
ARRAY
+2.7 TO +5.5VA
REFIO
FS ADJ
RSET
AD9774
EXTERNAL
REF
IREF =
VREFIO/RSET
AVDD
REFERENCE
CONTROL
AMPLIFIER
VREFIO
0.1 F
REFCOMP
Figure 28. External Reference Configuration
REFERENCE CONTROL AMPLIFIER
The AD9774 also contains an internal control amplifier that is
used to regulate the DAC’s full-scale output current, IOUTFS.
The control amplifier is configured as a V-I converter, as shown
in Figure 28, such that its current output, IREF, is determined by
the ratio of the VREFIO and an external resistor, RSET, as stated
in Equation 4. IREF is copied over to the segmented current
sources with the proper scaling factor to set IOUTFS as stated in
Equation 3.
The control amplifier allows a wide (10:1) adjustment span of
IOUTFS over a 2 mA to 20 mA range by setting IREF between
62.5
A and 625 A. The wide adjustment span of I
OUTFS
provides several application benefits. The first benefit relates
directly to the power dissipation of the AD9774, which is pro-
portional to IOUTFS (refer to the Power Dissipation section). The
second benefit relates to the 20 dB adjustment, which is useful
for system gain control purposes.
There are two methods by which IREF can be varied for a fixed
RSET. The first method is suitable for a single-supply system in
which the internal reference is disabled, and the common-mode
voltage of REFIO is varied over its compliance range of 1.25 V
to 0.10 V. REFIO can be driven by a single-supply amplifier or
DAC, thus allowing IREF to be varied for a fixed RSET. Since the
input impedance of REFIO is approximately 1 M
, a simple,
low cost R-2R ladder DAC configured in the voltage mode
topology may be used to control the gain. This circuit is shown
in Figure 30 using the AD7524 and an external 1.2 V reference,
the AD1580.
The second method may be used in a dual-supply system in
which the common-mode voltage of REFIO is fixed, and IREF is
varied by an external voltage, VGC, applied to RSET via an ampli-
fier. An example of this method is shown in Figure 29 in which
the internal reference is used to set the common-mode voltage
of the control amplifier to 1.20 V. The external voltage, VGC, is
referenced to ACOM and should not exceed 1.2 V. The value of
RSET is such that IREFMAX and IREFMIN do not exceed 62.5 A
and 625
A, respectively. The associated equations in Figure 29
can be used to determine the value of RSET.
50pF
+1.2V REF
AVDD
REFLO
CURRENT
SOURCE
ARRAY
+2.7 TO +5.5VA
REFIO
FSADJ
RSET
AD9774
IREF
VGC
1 F
IREF = (1.2–VGC)/RSET
WITH VGC
VREFIO AND 62.5 A
IREF
625A
0.1 F
REFCOMP
Figure 29. Dual Supply Gain Control Circuit
ANALOG OUTPUTS
The AD9774 produces two complementary current outputs,
IOUTA and IOUTB, which may be configured for single-end or
differential operation. IOUTA and IOUTB can be converted
into complementary single-ended voltage outputs, VOUTA and
VOUTB, via a load resistor, RLOAD, as described in the DAC
Transfer Function section by Equations 5 through 8. The
differential voltage, VDIFF, existing between VOUTA and VOUTB,
can also be converted to a single-ended voltage via a transformer
or differential amplifier configuration.
Figure 31 shows the equivalent analog output circuit of the
AD9774 consisting of a parallel combination of PMOS differen-
tial current switches associated with each segmented current
source. The output impedance of IOUTA and IOUTB is deter-
mined by the equivalent parallel combination of the PMOS
switches and is typically 100 k
in parallel with 5 pF. Due to
the nature of a PMOS device, the output impedance is also
slightly dependent on the output voltage (i.e., VOUTA and VOUTB)
and, to a lesser extent, the analog supply voltage, AVDD, and
full-scale current, IOUTFS. Although the output impedance’s
signal dependency can be a source of dc nonlinearity and ac linear-
ity (i.e., distortion), its effects can be limited if certain precau-
tions are noted.
1.2V
50pF
+1.2V REF
AVDD
REFLO
CURRENT
SOURCE
ARRAY
+2.7 TO +5.5VA
REFIO
FSADJ
RSET
AD9774
IREF =
VREF/RSET
AVDD
VREF
VDD
RFB
OUT1
OUT2
AGND
DB7–DB0
AD7524
AD1580
0.1V TO 1.2V
0.1 F
REFCOMP
Figure 30. Single Supply Gain Control Circuit
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