- 您现在的位置：买卖IC网 > PDF目录16826 > AD9858/PCBZ (Analog Devices Inc)BOARD EVAL FOR AD9858 PDF资料下载
参数资料
| 型号： | AD9858/PCBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 31/32页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9858 |
| 产品培训模块： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 设计资源： | Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109) |
| 标准包装： | 1 |
| 主要目的： | 计时，直接数字合成（DDS） |
| 已用 IC / 零件： | AD9858/TL |
| 已供物品： | 板 |
| 其它名称： | AD9858/PCB AD9858/PCB-ND |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页当前第31页第32页
AD9858
Rev. C | Page 8 of 32
Pin No.
Mnemonic
I/O
Description
17
SDO
O
This is valid for serial programming mode only. When operating the I/O port as a 3-wire
serial port, this pin serves as a unidirectional serial data output pin. When operated as a 2-wire
serial port, this pin is unused.
18
SDIO
I/O
This is valid for serial programming mode only. When operating the I/O port as a 3-wire serial
port, this pin is the serial data input. When operated as a 2-wire serial port, this pin is the
bidirectional serial data pin.
19
WR/SCLK
I
When the I/O port is configured for parallel programming mode, this pin functions as an active
low write pulse (WR). When configured for serial programming mode, this pin functions as the
serial data clock (SCLK).
22
RD/CS
I
When the I/O port is configured for parallel programming mode, this pin functions as an active
low read pulse (RD). When configured for serial programming mode, this pin functions as an
active low chip select (CS) that allows multiple devices to share the serial bus.
29, 30, 37 to 39,
41, 42, 49, 50, 52,
69, 74, 80, 85, 87, 88
AGND
I
Analog Ground.
31, 32, 35, 36,
40, 43, 44, 47,
48, 51, 70, 73,
77, 86, 89, 90
AVDD
I
Analog Supply Voltage.
33
REFCLK
I
Reference Clock Complementary Input. When the REFCLK port operates in single-ended mode,
REFCLK should be decoupled to AVDD with a 0.1 μF capacitor.
34
REFCLK
I
Reference Clock Input.
45
LO
I
Mixer Local Oscillator (LO) Complementary Input. When the LO port operates in single-ended
mode, LO should be decoupled to AVDD with a 0.1 μF capacitor.
46
LO
I
Mixer Local Oscillator (LO) Input.
53
RF
I
Analog Mixer RF Complementary Input. When the RF port operates in single-ended mode,
RF should be decoupled to AVDD with a 0.1 μF capacitor.
54
RF
I
Analog Mixer RF Input.
55
IF
O
Analog Mixer IF Output.
56
IF
O
Analog Mixer IF Complementary Output.
57
PFD
I
Phase Frequency Detector Complementary Input. When the PFD port operates in single-ended
mode, PFD should be decoupled to AVDD with a 0.1 μF capacitor.
58
PFD
I
Phase Frequency Detector Input.
59, 60, 75, 76
NC
No Connection.
61
CPISET
I
Charge Pump Output Current Control. A resistor connected from CPISET to CPGND establishes
the reference current for the charge pump.
62, 67
CPVDD
I
Charge Pump Supply Voltage.
63, 68
CPGND
I
Charge Pump Ground.
64
CPFL
O
Charge Pump Fast Lock Output.
65, 66
CP
O
Charge Pump Output.
71
DIV
I
Phase Frequency Detector Feedback Input.
72
DIV
I
Phase Frequency Detector Feedback Complementary Input. When the DIV port operates in
single-ended mode, DIV should be decoupled to AVDD with a 0.1 μF capacitor.
78
DACBP
DAC Baseline Decoupling Pin. Typically bypassed to Pin 77 with a 0.1 μF capacitor.
79
DACISET
I
A resistor connected from DACISET to AGND establishes the reference current for the DAC.
81, 82
IOUT
O
DAC Output.
83, 84
IOUT
O
DAC Complementary Output.
91
SPSELECT
I
I/O Port Serial/Parallel Programming Mode Select Pin. Logic 0 is serial programming mode, and
Logic 1 is parallel programming mode.
92
RESET
I
Active High Hardware Reset Pin. Assertion of the RESET pin forces the AD9858 to its default
operating conditions.
97, 98
PS0, PS1
I
Used to select one of the four internal profiles. These pins are synchronous to the SYNCLK output.
99
FUD
I
Frequency Update. The rising edge transfers the contents of the internal buffer registers to the
memory registers. This pin is synchronous to the SYNCLK output.
100
SYNCLK
O
Clock Output Pin. Serves as a synchronizer for external hardware. SYNCLK runs at REFCLK/8.
EPAD
Exposed paddle must be soldered to ground.
相关PDF资料 |
PDF描述 |
|---|---|
| AD9956-VCO/PCBZ | BOARD EVAL 14BIT 1.8V 48LFCSP |
| GEM22DRKF | CONN EDGECARD 44POS DIP .156 SLD |
| 362A024-4/86-0 | BOOT MOLDED |
| AD9956/PCBZ | BOARD EVAL FOR AD9956 |
| 0210391089 | CABLE JUMPER 1MM .203M 37POS |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9858TLPCB | 制造商:AD 制造商全称:Analog Devices 功能描述:1 GSPS Direct Digital Synthesizer |
| AD9858XSV | 制造商:Analog Devices 功能描述: |
| AD9859 | 制造商:AD 制造商全称:Analog Devices 功能描述:400 MSPS, 10-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| AD9859/PCB | 制造商:Analog Devices 功能描述:NCO, 400MSPS 10 BIT, 1.8V CMOS DIRECT DGTL SYNTHESIZER - Bulk |
| AD9859/PCBZ | 功能描述:BOARD EVAL FOR AD9859 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:AgileRF™ 标准包装:1 系列:- 主要目的:电信，线路接口单元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要属性:T1/J1/E1 LIU 次要属性:- 已供物品:板，电源，线缆，CD 其它名称:82EBV2081 |
发布紧急采购，3分钟左右您将得到回复。