- 您现在的位置：买卖IC网 > PDF目录16826 > AD9858/PCBZ (Analog Devices Inc)BOARD EVAL FOR AD9858 PDF资料下载
参数资料
| 型号： | AD9858/PCBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 9/32页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9858 |
| 产品培训模块： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 设计资源： | Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109) |
| 标准包装： | 1 |
| 主要目的： | 计时，直接数字合成（DDS） |
| 已用 IC / 零件： | AD9858/TL |
| 已供物品： | 板 |
| 其它名称： | AD9858/PCB AD9858/PCB-ND |
第1页第2页第3页第4页第5页第6页第7页第8页当前第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页
AD9858
Rev. C | Page 17 of 32
Single-Tone Mode
When the decimal number is calculated, it must be rounded to
an integer and converted to a 32-bit binary value. The frequency
resolution of the AD9858 is 0.233 Hz when the SYSCLK is 1 GHz.
When in single-tone mode, the AD9858 generates a signal, or
tone, of a single desired frequency. This frequency is set by the
value loaded by the user into the chip’s FTW register. This
frequency can be between 0 Hz and somewhat below one-half
of the DAC sampling frequency (SYSCLK). One-half of the
sampling frequency is commonly called the Nyquist frequency.
The practical upper limit to the fundamental frequency range of
a DDS is determined by the characteristics of the external low-
pass filter, known as the reconstruction filter, which must follow
the DAC output of the DDS. This filter reconstructs the desired
analog sine wave output signal from the stream of sampled
amplitude values output by the DAC at the sample rate (SYSCLK).
Frequency Sweeping Mode
The AD9858 provides an automated frequency sweeping capability.
This allows the AD9858 to generate frequency swept signals for
chirped radar or other applications. The AD9858 includes features
that automate much of the task of executing frequency sweeps.
The frequency sweep feature is implemented through the use
of a frequency accumulator (not to be confused with the phase
accumulator). The frequency accumulator repeatedly adds an
incremental quantity to the current FTW, thereby creating new
instantaneous frequency tuning words, causing the frequency
generated by the DDS to change with time. The frequency
increment, or step size, is loaded into the delta frequency
tuning word (DFTW) register. The rate at which the frequency
is incremented is set by the delta frequency ramp rate word
(DFRRW) register. Together these registers enable the AD9858 to
sweep from a beginning frequency set by the FTW, upwards or
downwards, at a desired rate and frequency step size. The result is
a linear frequency sweep or chirp.
A DDS is a sampled data system. As the fundamental frequency
of the DDS approaches the Nyquist frequency, the lower first
image approaches the Nyquist frequency from above. As the
fundamental frequency approaches the Nyquist frequency, it
becomes difficult, and finally impossible, to design and construct a
low-pass filter that provides adequate attenuation for the first
image frequency component.
The maximum usable frequency in the fundamental range of
the DDS is typically between 40% and 45% relative to the SYSCLK
frequency, depending on the reconstruction filter. With a 1 GHz
SYSCLK, the AD9858 is capable of producing maximum output
frequencies of between 400 MHz and 450 MHz, depending on the
reconstruction filter and the application system requirements.
The DFRRW functions as a countdown timer, in which the
value of the DFRRW is decremented at the rate of SYSCLK/8.
This means that the most rapid frequency word update occurs
when a value of 1 is loaded into the DFRRW and results in a
frequency increment at 1/8 of the SYSCLK rate. With a SYSCLK
of 1 GHz, the frequency can be incremented at a maximum rate
of 125 MHz (DFRRW = 1). The DFTW must specify whether
the frequency sweep should proceed up or down from the starting
frequency (FTW). Therefore, the DFTW is expressed as a twos
complement binary value, in which positive indicates up and
negative indicates down.
For a desired output frequency (fOUT) and sampling rate (SYSCLK),
the FTW of the AD9858 is calculated by
FTW = (fOUT × 2N)/SYSCLK
where:
N is the phase accumulator resolution in bits (32 in the AD9858).
SYSCLK is in Hertz.
FTW is a decimal number.
40ns
80ns
TIME
F
RE
Q
UE
NCY
120ns
160ns
DELTA FREQUENCY RAMP RATE WORD (≥8ns)
8ns
16ns
TIME
F
RE
Q
UE
NCY
24ns
32ns
DELTA FREQUENCY TUNING WORD
03
16
6-
0
35
Figure 32. Frequency vs. Time Plots for a Given Sweep Profile
相关PDF资料 |
PDF描述 |
|---|---|
| AD9956-VCO/PCBZ | BOARD EVAL 14BIT 1.8V 48LFCSP |
| GEM22DRKF | CONN EDGECARD 44POS DIP .156 SLD |
| 362A024-4/86-0 | BOOT MOLDED |
| AD9956/PCBZ | BOARD EVAL FOR AD9956 |
| 0210391089 | CABLE JUMPER 1MM .203M 37POS |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9858TLPCB | 制造商:AD 制造商全称:Analog Devices 功能描述:1 GSPS Direct Digital Synthesizer |
| AD9858XSV | 制造商:Analog Devices 功能描述: |
| AD9859 | 制造商:AD 制造商全称:Analog Devices 功能描述:400 MSPS, 10-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| AD9859/PCB | 制造商:Analog Devices 功能描述:NCO, 400MSPS 10 BIT, 1.8V CMOS DIRECT DGTL SYNTHESIZER - Bulk |
| AD9859/PCBZ | 功能描述:BOARD EVAL FOR AD9859 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:AgileRF™ 标准包装:1 系列:- 主要目的:电信，线路接口单元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要属性:T1/J1/E1 LIU 次要属性:- 已供物品:板，电源，线缆，CD 其它名称:82EBV2081 |
发布紧急采购，3分钟左右您将得到回复。