参数资料
型号: AD9858/PCBZ
厂商: Analog Devices Inc
文件页数: 8/32页
文件大小: 0K
描述: BOARD EVAL FOR AD9858
产品培训模块: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
设计资源: Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109)
标准包装: 1
主要目的: 计时,直接数字合成(DDS)
已用 IC / 零件: AD9858/TL
已供物品:
其它名称: AD9858/PCB
AD9858/PCB-ND
AD9858
Rev. C | Page 16 of 32
When frequency detection occurs, the loop is closed and the
loop is locked based on the current programmed for the wide
closed-loop mode. It is important that the loop be designed for
closed-loop stability while in the wide closed-loop mode. In this
mode, less phase margin can usually be tolerated, because this
mode is only used to enhance the lock time but is not used in
the locked free running state. When the wide closed-loop mode
achieves phase lock as determined by an internal lock detector,
the phase detector/charge pump transitions into the final
closed-loop state. If no wide closed-loop current is programmed,
the loop transitions directly from the frequency detect mode
into the final closed-loop state. In the final closed-loop state,
optimize the loop characteristics for the desired free running
loop bandwidth.
The frequency detect mode is primarily useful in offset or
translation loop applications where the phase detector inputs
are more likely to detect large frequency transitions. For loop
applications with significant amounts of division in the feedback
loop, the frequency detection mode may not activate. This is due
to the limited amount of frequency difference that is experienced
at the phase detector inputs. For these applications, the primary
means of accelerating the frequency settling time is to design
the loop to acquire lock with the wide closed-loop setting and
then switch to the final closed-loop setting.
As previously mentioned, care should be taken when planning
for a large transition using the frequency detect mode to ensure
that the charge pump does not cause the VCO to overshoot the
closed-loop lock range, because cycle slipping can occur, which
results in extended delays. Figure 30 shows two system responses.
In the first response, the charge pump output current is
maximized during the frequency detect mode so that, after
152 clock cycles, the VCO voltage exceeds the closed-loop lock
range. The second system response provides less current during
the frequency detect mode. Although this results in a longer
delay in approaching the closed-loop lock range, because the
system does not exceed the closed-loop range, the fast locking
logic shifts the charge pump into intermediary closed-loop
mode, resulting in a shorter overall frequency switching time.
TIME
VC
O
VOLTA
GE
03166-A
-033
Figure 30. Typical Charge Pump Responses
Analog Mixer
The analog mixer is included for translation loops, also known
as offset loops. The radio frequency (RF) and local oscillator
(LO) inputs are designed to operate at frequencies up to 2 GHz.
Both inputs are differential analog input stages. Both input stages
are internally dc biased and should be connected through an
external ac coupling mechanism. The expected input level is
in the range of 800 mV p-p (differential). The intermediate
frequency (IF) output is a differential analog output stage
designed to operate at frequencies less than 400 MHz. This
mixer is based on the Gilbert cell architecture.
MODES OF OPERATION
The AD9858 DDS section has three modes of operation: single
tone, frequency sweeping, and full sleep. The RF building blocks
(PFD, CP, and mixer) can be active or powered down, used or
unused, in the active modes.
In the single-tone mode, the device generates a single output
frequency determined by a 32-bit word (frequency tuning word,
FTW) loaded to an internal register. This frequency can be changed
as desired, and frequency hopping can be accomplished at a rate
limited only by the time required to update the appropriate
registers. If even faster hopping is needed, the four profiles
allow rapid hopping among the four frequencies stored in them
by means of external select pins.
The frequency sweeping mode allows for the automation of most of
the frequency sweeping task, making chirp and other frequency
sweeping applications possible without multiple register operations
via the I/O port.
In whatever mode the device is operating, changes in frequency
are phase continuous (they do not cause discontinuities in the
phase of the output signal). The first phase value after a frequency
change is an increment of the last phase value before the change,
but at the phase increment value (FTW) of the new tuning
word. (This is not the same as phase coherent over frequency
changes; see Figure 31.)
REFERENCE SIGNAL
fREF = A
fOUT = 2A
fOUT = A
fOUT = 2A
fOUT = A
PHASE COHERENT
PHASE CONTINUOUS
WHERE θ = PHASE OF OUTPUT SIGNAL, Ф = PHASE AT TIME OF FIRST FREQUENCY
TRANSITION, AND Ф' = PHASE AT TIME OF SECOND FREQUENCY TRANSITION.
θ = 2θREFФ
θ = 2θREF+Ф + Ф'
θ = 2θREF
θ = θREF
03
166-
034
Figure 31. Difference Between a Phase Continuous Frequency Change and
a Phase Coherent Frequency Change
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