- 您现在的位置：买卖IC网 > PDF目录11804 > AD9887AKSZ-170 (Analog Devices Inc)IC INTRFACE ANALOG/DVI 160-MQFP PDF资料下载
参数资料
| 型号： | AD9887AKSZ-170 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 24/40页 |
| 文件大小： | 0K |
| 描述： | IC INTRFACE ANALOG/DVI 160-MQFP |
| 标准包装： | 24 |
| 应用： | 图形卡，VGA 接口 |
| 接口： | 模拟和数字 |
| 电源电压： | 3.15 V ~ 3.45 V |
| 封装/外壳： | 160-BQFP |
| 供应商设备封装： | 160-MQFP（28x28） |
| 包装： | 托盘 |
| 安装类型： | 表面贴装 |
| 产品目录页面： | 788 (CN2011-ZH PDF) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页当前第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页
REV. 0
–30–
AD9887
06
7–0
Clamp Duration
An 8-bit register that sets the duration of the internally
generated clamp.
When EXTCLMP = 0, a clamp signal is generated inter-
nally, at a position established by the clamp placement
and for a duration set by the clamp duration. Clamping is
started (clamp placement) pixel periods after the trailing
edge of Hsync, and continues for (clamp duration) pixel
periods. The clamp duration may be programmed to any
value between 1 and 255. A value of 0 is not supported.
For the best results, the clamp duration should be set to
include the majority of the black reference signal time that
follows the Hsync signal trailing edge. Insufcient clamp-
ing time can produce brightness changes at the top of the
screen, and a slow recovery from large changes in the
Average Picture Level (APL), or brightness.
When EXTCLMP = 1, this register is ignored.
Hsync Pulsewidth
07
7–0
Hsync Output Pulsewidth
An 8-bit register that sets the duration of the Hsync
output pulse.
The leading edge of the Hsync output is triggered by the
internally generated, phase-adjusted PLL feedback clock.
The AD9887 then counts a number of pixel clocks equal
to the value in this register. This triggers the trailing edge
of the Hsync output, which is also phase-adjusted.
INPUT GAIN
08
7–0
Red Channel Gain Adjust
An 8-bit word that sets the gain of the RED channel.
The AD9887 can accommodate input signals with a
full-scale range of between 0.5 V and 1.5 V p-p. Setting
REDGAIN to 255 corresponds to an input range of 1.0 V.
A REDGAIN of 0 establishes an input range of 0.5 V.
Note that INCREASING REDGAIN results in the picture
having LESS CONTRAST (the input signal uses fewer
of the available converter codes). See Figure 3.
09
7–0
Green Channel Gain Adjust
An 8-bit word that sets the gain of the GREEN channel.
See REDGAIN (08).
0A
7–0
Blue Channel Gain Adjust
An 8-bit word that sets the gain of the BLUE channel.
See REDGAIN (08).
INPUT OFFSET
0B
7–1
Red Channel Offset Adjust
A 7-bit offset binary word that sets the dc offset of the RED
channel. One LSB of offset adjustment equals approximately
one LSB change in the ADC offset. Therefore, the absolute
magnitude of the offset adjustment scales as the gain of the
channel is changed. A nominal setting of 63 results in the
channel nominally clamping the back porch (during the
clamping interval) to Code 00. An offset setting of 127
results in the channel clamping to Code 63 of the ADC. An
offset setting of 0 clamps to code –63 (off the bottom of
the range). Increasing the value of Red Offset DECREASES
the brightness of the channel.
0C
7–1
Green Channel Offset Adjust
A 7-bit offset binary word that sets the dc offset of the
GREEN channel. See REDOFST (0B).
0D
7–1
Blue Channel Offset Adjust
A 7-bit offset binary word that sets the dc offset of the
GREEN channel. See REDOFST (0B).
MODE CONTROL 1
0E
7
Channel Mode
A bit that determines whether all pixels are presented to a
single port (A), or alternating pixels are demultiplexed to
Ports A and B.
Table XII. Channel Mode Settings
DEMUX
Function
0
All Data Goes to Port A
1
Alternate Pixels Go to Port A and Port B
When DEMUX = 0, Port B outputs are in a high-impedance
state. The maximum data rate for single port mode is
100 MHz. The timing diagrams show the effects of this option.
The power-up default value is 1.
0E
6
Output Mode
A bit that determines whether all pixels are presented to
Port A and Port B simultaneously on every second
DATACK rising edge, or alternately on port A and Port B
on successive DATACK rising edges.
Table XIII. Output Mode Settings
PARALLEL
Function
0
Data Is Interleaved
1
Data Is Simultaneous On Every Other
Data Clock
When in single port mode (DEMUX = 0), this bit is ig-
nored. The timing diagrams show the effects of this option.
The power-up default value is PARALLEL = 1.
0E
5
Output Port Phase
One bit that determines whether even pixels or odd pixels
go to Port A.
Table XIV. Output Port Phase Settings
OUTPHASE
First Pixel After Hsync
0
Port B
1
Port A
In normal operation (OUTPHASE = 1), when operating
in dual-port output mode (DEMUX = 1), the rst sample
after the Hsync leading edge is presented at Port A. Every
subsequent ODD sample appears at Port A. All EVEN
samples go to Port B.
When OUTPHASE = 0, these ports are reversed and the
rst sample goes to Port B.
OBSOLETE
相关PDF资料 |
PDF描述 |
|---|---|
| VE-B5T-IX-F2 | CONVERTER MOD DC/DC 6.5V 75W |
| VE-B5T-IX-F1 | CONVERTER MOD DC/DC 6.5V 75W |
| AT89C51CC03C-RDRIM | IC 8051 MCU FLASH 64K 64VQFP |
| D38999/24FC8SN | CONN RCPT 8POS JAM NUT W/SCKT |
| MS27473T18A35S | CONN PLUG 66POS STRAIGHT W/SCKT |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9887AKSZ-170 | 制造商:Analog Devices 功能描述:IC DUAL DISPLAY INTERFACE |
| AD9887AKSZ-1701 | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual Interface for Flat Panel Display |
| AD9887APCB | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
| AD9887KS-100 | 制造商:Analog Devices 功能描述:Interface for Flat Panel Display 160-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:DUAL A/D INTERFACE FOR FLAT PANEL - Bulk |
| AD9887KS-140 | 制造商:Analog Devices 功能描述:Interface for Flat Panel Display 160-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:DUAL A/D INTERFACE FOR FLAT PANEL - Bulk 制造商:Analog Devices 功能描述:IC INTERFACE DUAL DISPLAY |
发布紧急采购，3分钟左右您将得到回复。