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参数资料
型号： AD9887AKSZ-170
厂商： Analog Devices Inc
文件页数： 34/40页
文件大小： 0K
描述： IC INTRFACE ANALOG/DVI 160-MQFP
标准包装： 24
应用： 图形卡，VGA 接口
接口： 模拟和数字
电源电压： 3.15 V ~ 3.45 V
封装/外壳： 160-BQFP
供应商设备封装： 160-MQFP（28x28）
包装： 托盘
安装类型： 表面贴装
产品目录页面： 788 (CN2011-ZH PDF)
REV. 0
–4–
AD9887–SPECIFICATIONS
DIGITAL INTERFACE
Test
AD9887KS
Parameter
Conditions
Level
Min
Typ
Max
Unit
RESOLUTION
8
Bits
DC DIGITAL I/O SPECIFICATIONS
High-Level Input Voltage, (VIH)
VI
2.6
V
Low-Level Input Voltage, (VIL)
VI
0.8
V
High-Level Output Voltage, (VOH)
VI
2.4
V
Low-Level Output Voltage, (VOL)
VI
0.4
V
Input Clamp Voltage, (VCINL)(ICL = –18 mA)
IV
GND – 0.8
V
Input Clamp Voltage, (VCIPL)(ICL = +18 mA)
IV
VDD + 0.8
V
Output Clamp Voltage, (VCONL)(ICL = –18 mA)
IV
GND – 0.8
V
Output Clamp Voltage, (VCOPL)(ICL = +18 mA)
IV
VDD + 0.8
V
Output Leakage Current, (IOL)
(High Impedance)
IV
–10
+10
A
DC SPECIFICATIONS
Output High Drive
Output Drive = High
IV
13
mA
(IOHD) (VOUT = VOH)
Output Drive = Med
IV
8
mA
Output Drive = Low
IV
5
mA
Output Drive = High
IV
–9
mA
(IOLD) (VOUT = VOL)
Output Drive = Med
IV
–7
mA
Output Drive = Low
IV
–5
mA
Output Drive = High
IV
25
mA
(VOHC) (VOUT = VOH)
Output Drive = Med
IV
12
mA
Output Drive = Low
IV
8
mA
DATACK Low Drive
Output Drive = High
IV
–25
mA
(VOLC) (VOUT = VOL)
Output Drive = Med
IV
–19
mA
Output Drive = Low
IV
–8
mA
Differential Input Voltage Single-Ended Amplitude
IV
75
800
mV
POWER SUPPLY
VD Supply Voltage
IV
3.0
3.3
3.6
V
VDD Supply Voltage
Minimum Value for 2 Pixels per
Clock Mode
IV
2.2
3.3
3.6
V
PVD Supply Voltage
IV
3.0
3.3
3.6
V
VD Supply Current (Typical Pattern)
1
V
274
mA
VDD Supply Current (Typical Pattern)
1, 4
V38
mA
PVD Supply Current (Typical Pattern)
1
V21
mA
Total Supply Current (Typical Pattern)
1, 4
VI
362
mA
VD Supply Current (Worst-Case Pattern)
2
V
280
mA
VDD Supply Current (Worst-Case Pattern)
2, 4
V75
mA
PVD Supply Current (Worst-Case Pattern)
2
V21
mA
Total Supply Current (Worst-Case Pattern)
2, 4
VI
400
mA
Power-Down Supply Current (IPD)VI
13
25
mA
AC SPECIFICATIONS
Intrapair (+ to –) Differential Input Skew (TDPS)
IV
360
ps
Channel-to-Channel Differential Input Skew (TCCS)
IV
1.0
Clock
Period
Low-to-High Transition Time for Data and
Output Drive = High; CL = 10 pF
IV
2.0
ns
Controls (DLHT)
Output Drive = Med; CL = 7 pF
IV
3.0
ns
Output Drive = Low; CL = 5 pF
IV
3.4
ns
Low-to-High Transition Time for DATACK (DLHT)
Output Drive = High; CL = 10 pF
IV
1.3
ns
Output Drive = Med; CL = 7 pF
IV
1.9
ns
Output Drive = Low; CL = 5 pF
IV
2.5
ns
High-to-Low Transition Time for Data and
Output Drive = High; CL = 10 pF
IV
2.7
ns
Controls (DHLT)
Output Drive = Med; CL = 7 pF
IV
3.0
ns
Output Drive = Low; CL = 5 pF
IV
3.3
ns
(VD = 3.3 V, VDD = 3 V, Clock = Maximum)
OBSOLETE
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