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参数资料
| 型号： | AD9888KSZ-170 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/36页 |
| 文件大小： | 0K |
| 描述： | IC ANALOG INTRFC 170MSPS 128MQFP |
| 标准包装： | 1 |
| 应用： | 图形卡，VGA 接口 |
| 接口： | 2 线串口 |
| 电源电压： | 3 V ~ 3.6 V |
| 封装/外壳： | 128-BFQFP |
| 供应商设备封装： | 128-MQFP（14x20） |
| 包装： | 托盘 |
| 安装类型： | 表面贴装 |
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AD9888
Data Sheet
Rev. C | Page 22 of 36
Hex
Address
Read and
Write, or
Read Only
Bits
Default
Value
Register Name
Function
0x0F
R/W
[7:1]
0*******
Bit 7—clamp input signal source. Chooses between HSYNC and another
external signal to be used for clamping. Logic 0 = HSYNC; Logic 1 =
CLAMP.
*1******
Bit 6—clamp input signal polarity. Valid only with external CLAMP
signal. Logic 0 = active high; Logic 1 = active low.
**0*****
Bit 5—coast select. Logic 0 = the COAST input pin is used for the PLL
coast; Logic 1 = VSYNC is used for the PLL coast.
***0****
Bit 4—coast input polarity override. Logic 0 = polarity determined by
chip; Logic 1 = polarity set by Bit 3 in Register 0x0F.
****1***
Bit 3—coast input polarity. Changes polarity of external COAST signal.
Logic 0 = active low; Logic 1 = active high.
*****1**
Bit 2—seek mode override. Logic 1 = enable low power mode; Logic 0 =
disable low power mode.
******1*
Bit 1—PWRDN. Full chip power-down, active low. Logic 0 = full chip
power-down; Logic 1 = normal.
0x10
R/W
[7:0]
01111***
Sync-on-green
threshold
Bits[7:3]—Sync-on-green threshold. Sets the voltage level of the sync-
on-green slicer comparator.
*****0**
Bit 2—red clamp select. Logic 0 = clamp to ground; Logic 1 = clamp to
midscale (voltage at Pin 9).
******0*
Bit 1—blue clamp select. Logic 0 = clamp to ground; Logic 1 = clamp to
midscale (voltage at Pin 24).
*******0
Bit 0—must be set to 1 for proper operation.
0x11
R/W
[7:0]
00100000
Sync separator
threshold
Sync separator threshold. Sets how many internal 5 MHz clock periods
the sync separator counts before toggling high or low. Should be set to
a number greater than the maximum HSYNC or equalization pulse
width.
0x12
R/W
[7:0]
00000000
Pre-COAST
Pre-COAST. Sets the number of HSYNC periods before which COAST
becomes active prior to VSYNC.
0x13
R/W
[7:0]
00000000
Post-COAST
Post-COAST. Sets the number of HSYNC periods before which COAST
stays active following VSYNC.
0x14
RO
[7:0]
Sync detect
Bit 7—HSYNC detect. Logic 1 = HSYNC is present on the analog
interface; Logic 0 = HSYNC is not present on the analog interface.
Bit 6—active HSYNC (AHS). This bit indicates which analog HSYNC is
being used. Logic 0 = HSYNC input pin; Logic 1 = HSYNC from sync-on-
green.
Bit 5—detected HSYNC input polarity status. Logic 0 = active low;
Logic 1 = active high.
Bit 4—VSYNC detect. Logic 1 = VSYNC is present on the analog
interface; Logic 0 = VSYNC is not present on the analog interface.
Bit 3—active VSYNC (AVS). This bit indicates which analog VSYNC is
being used. Logic 0 = VSYNC input pin; Logic 1 = VSYNC from sync
separator.
Bit 2—detected VSYNC output polarity status. Logic 0 = active high;
Logic 1 = active low.
Bit 1—sync-on-green detect. Logic 1 = sync is present on the green
video input; Logic 0 = sync is not present on the green video input.
Bit 0—detected coast polarity status. Logic 0 = active low; Logic 1 =
active high.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9888KSZ-170 | 制造商:Analog Devices 功能描述:TV / Video IC |
| AD9888KSZ-205 | 制造商:Analog Devices 功能描述:205MHZ ANALOG GRAPHICS INTERFACE 制造商:Analog Devices 功能描述:IC ANALOG INTERFACE |
| AD9888KSZ-205KL1 | 制造商:Analog Devices 功能描述:- Rail/Tube |
| AD9889 | 制造商:Analog Devices 功能描述:- Bulk |
| AD9889A | 制造商:AD 制造商全称:Analog Devices 功能描述:High Performance HDMI/DVI Transmitter |
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