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| 型号： | AD9888KSZ-170 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 2/36页 |
| 文件大小： | 0K |
| 描述： | IC ANALOG INTRFC 170MSPS 128MQFP |
| 标准包装： | 1 |
| 应用： | 图形卡，VGA 接口 |
| 接口： | 2 线串口 |
| 电源电压： | 3 V ~ 3.6 V |
| 封装/外壳： | 128-BFQFP |
| 供应商设备封装： | 128-MQFP（14x20） |
| 包装： | 托盘 |
| 安装类型： | 表面贴装 |
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AD9888
Data Sheet
Rev. C | Page 10 of 36
Mnemonic
Description
Outputs
DRA[7:0]
Data Output, Red Channel, Port A.
DRB[7:0]
Data Output, Red Channel, Port B.
DGA[7:0]
Data Output, Green Channel, Port A.
DGB[7:0]
Data Output, Green Channel, Port B.
DBA[7:0]
Data Output, Blue Channel, Port A.
DBB[7:0]
Data Output, Blue Channel, Port B.
Each channel has two ports. When the part is operated in single-channel mode (channel mode bit (Register 0x15, Bit 7) = 0),
all data is presented to Port A, and Port B is placed in a high impedance state. Programming the channel mode bit to 1
establishes dual-channel mode, where pixels are alternately presented to Port A and Port B of each channel. These appear
simultaneously; two pixels are presented at the time of every second input pixel when the output mode bit (Register 0x15,
Bit 6) is set to 1 (parallel mode). When the output mode bit is set to 0, pixel data appear alternately on the two ports, one
new sample with each incoming pixel (interleaved mode). In dual-channel mode, the first pixel after HSYNC is routed to
Port A. The second pixel goes to Port B, the third to Port A, and so on. This can be reversed by setting the A/B invert control bit
(Register 0x15, Bit 5) to 1. The delay from the pixel sampling time to the output is fixed. When the sampling time is changed by
adjusting the clock phase adjust register (Register 0x04, Bits[7:3]), the output timing is shifted as well. The DATACK, DATACK,
and HSOUT outputs are also moved; therefore, the timing relationship among the signals is maintained.
DATACK,
DATACK
Data Output Clock, Data Output Clock Complement.
These are differential data clock output signals to be used to strobe the output data and HSOUT into external logic. They
are produced by the internal clock generator and are synchronous with the internal pixel sampling clock. When the AD9888 is
operated in single-channel mode, the output frequency is equal to the pixel sampling frequency. When operated in dual-
channel mode, the clock frequency is half the pixel frequency, as is the output data frequency. When the sampling time is
changed by adjusting the clock phase adjust register (Register 0x04, Bits[7:3]), the output timing is shifted as well. The data,
DATACK, DATACK, and HSOUT outputs are all moved; therefore, the timing relationship among the signals is maintained.
Either or both signals can be used, depending on the timing mode and interface design used.
HSOUT
Horizontal Sync Output.
This is a reconstructed, phase-aligned version of the HSYNC input. Both the polarity and duration of this output can be
programmed via serial bus registers. By maintaining alignment with DATACK, DATACK, and data, data timing with respect
to horizontal sync can always be determined.
VSOUT
Verical Sync Output.
SOGOUT
Sync-on-Green (SOG) Slicer Output.
This pin can be programmed to output either the sync-on-green slicer comparator or an unprocessed but delayed version
of the HSYNC input. See the sync processing block diagram (Figure 27) to view how this pin is connected. Note that other
than slicing off SOG, the output from this pin receives no other additional processing on the AD9888. VSYNC separation is
performed via the sync separator.
REF BYPASS
Internal Reference Bypass.
The absolute accuracy of this reference is ±4%, and the temperature coefficient is ±50 ppm, which is adequate for most
AD9888 applications. If higher accuracy is required, an external reference can be employed instead.
RMIDSCV
Red Channel Midscale Voltage Bypass.
BMIDSCV
Blue Channel Midscale Voltage Bypass.
These bypasses for the internal midscale voltage references should each be connected to ground through 0.1 μF capacitors.
The exact voltage varies with the gain setting of the blue channel.
FILT
External Filter Connection. For proper operation, the internal PLL that generates the pixel clock requires an external filter.
Connect the filter shown in Figure 9 to this pin. For optimal performance, minimize noise and parasitics on this node.
Power Supply
VD
Main Power Supply. These pins supply power to the main elements of the circuit. This supply should be as quiet and
filtered as possible.
VDD
Digital Output Power Supply.
A large number of output pins (up to 52) switching at high speed (up to 110 MHz) generates significant power supply
transients (noise). These supply pins are identified separately from the VD pins; therefore, special care must be taken to
minimize output noise transferred into the sensitive analog circuitry. If the AD9888 is interfacing with lower voltage logic,
VDD can be connected to a lower supply voltage (as low as 2.5 V) for compatibility.
PVD
Clock Generator Power Supply.
The most sensitive portion of the AD9888 is the clock generation circuitry. These pins provide power to the PLL generated pixel
clock and help the user design for optimal performance. The designer should provide noise-free power to these pins.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9888KSZ-170 | 制造商:Analog Devices 功能描述:TV / Video IC |
| AD9888KSZ-205 | 制造商:Analog Devices 功能描述:205MHZ ANALOG GRAPHICS INTERFACE 制造商:Analog Devices 功能描述:IC ANALOG INTERFACE |
| AD9888KSZ-205KL1 | 制造商:Analog Devices 功能描述:- Rail/Tube |
| AD9889 | 制造商:Analog Devices 功能描述:- Bulk |
| AD9889A | 制造商:AD 制造商全称:Analog Devices 功能描述:High Performance HDMI/DVI Transmitter |
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