- 您现在的位置：买卖IC网 > PDF目录1894 > AD9888KSZ-170 (Analog Devices Inc)IC ANALOG INTRFC 170MSPS 128MQFP PDF资料下载
参数资料
| 型号： | AD9888KSZ-170 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 19/36页 |
| 文件大小： | 0K |
| 描述： | IC ANALOG INTRFC 170MSPS 128MQFP |
| 标准包装： | 1 |
| 应用： | 图形卡，VGA 接口 |
| 接口： | 2 线串口 |
| 电源电压： | 3 V ~ 3.6 V |
| 封装/外壳： | 128-BFQFP |
| 供应商设备封装： | 128-MQFP（14x20） |
| 包装： | 托盘 |
| 安装类型： | 表面贴装 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页当前第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页
AD9888
Data Sheet
Rev. C | Page 26 of 36
Address 0x0E[5]—HSYNC Output Polarity
This bit determines the polarity of the HSYNC output and the
SOG output (see Table 13).
Table 13. HSYNC Output Polarity Settings
HSYNC Output Polarity Setting
Function
0 (default)
Logic 1 (positive polarity)
1
Logic 0 (negative polarity)
Address 0x0E[4]—Active HSYNC Override
This bit is used to override the automatic HSYNC selection. To
initiate this override, set this bit to Logic 1. When overriding the
automatic HSYNC selection, the active HSYNC is set via Bit 3
in this register.
Table 14. Active HSYNC Override Settings
Active HSYNC Override Setting
Function
0 (default)
Bit 6 in Register 0x14 deter-
mines the active interface.
1
Override, Bit 3 determines
the active interface.
Address 0x0E[3]—Active HSYNC Select
This bit is used under two conditions. It is used to select the
active HSYNC when the override bit (Register 0x0E, Bit 4) is
set. Alternatively, it is used to determine the active HSYNC
when the override bit is not set but both HSYNCs are detected.
Table 15. Active HSYNC Select Settings
Active HSYNC Select Setting
Function
0 (default)
HSYNC input
1
Sync-on-green input
Address 0x0E[2]—VSYNC Output Invert
This bit inverts the polarity of the VSYNC output (see Table 16).
Table 16. VSYNC Output Polarity Settings
VSYNC Output Invert Setting
Function
0 (default)
Invert
1
Do not invert
Address 0x0E[1]—Active VSYNC Override
This bit is used to override the automatic VSYNC selection. To
initiate this override, set this bit to Logic 1. When overriding
the automatic VSYNC selection, the active interface is set via
Bit 0 in this register.
Table 17. Active VSYNC Override Settings
Active VSYNC Override Setting
Function
0 (default)
Bit 3 in Register 0x14 deter-
mines the active VSYNC.
1
Override, Bit 0 determines
the active VSYNC.
Address 0x0E[0]—Active VSYNC Select
This bit is used to select the active VSYNC when the override
bit (Register 0x0E, Bit 1) is set.
Table 18. Active VSYNC Select Settings
Active VSYNC Select Setting
Function
0 (default)
VSYNC input
1
Sync separator output
INPUT CONTROL
Address 0x0F[7]—Clamp Input Signal Source
This bit determines the source of clamp timing.
Table 19. Clamp Input Signal Source Settings
Clamp Input Signal Source Setting
Function
0 (default)
Internally generated
clamp
1
Externally provided
clamp signal
A 0 enables the clamp timing circuitry controlled by clamp
placement and clamp duration. The clamp position and
duration is counted from the trailing edge of HSYNC.
A 1 enables the external CLAMP input pin. The three channels are
clamped when the CLAMP signal is active. The polarity of CLAMP
is determined by the clamp input signal polarity bit (Register 0x0F,
Bit 6).
Address 0x0F[6]—Clamp Input Signal Polarity
This bit determines the polarity of the externally provided
CLAMP signal.
Table 20. Clamp Input Signal Polarity Settings
CLAMP Input Signal Polarity Setting
Function
0
Active high
1 (default)
Active low
A Logic 1 means the circuit clamps when CLAMP is low and
passes the signal to the ADC when CLAMP is high.
A Logic 0 means the circuit clamps when CLAMP is high and
passes the signal to the ADC when CLAMP is low.
Address 0x0F[5]—Coast Select
This bit is used to select the active coast source. The choices are
the COAST input pin or VSYNC. If VSYNC is selected, users
must decide whether to use the VSYNC input pin or the output
from the sync separator (Register 0x0E, Bit 1 and Bit 0).
Table 21. Coast Source Selection Settings
Coast Select Setting
Function
0 (default)
COAST input pin
1
VSYNC (must choose
VSYNC input pin or
output from sync
separator)
相关PDF资料 |
PDF描述 |
|---|---|
| AD9895KBCZRL | IC CCD SIGNAL PROC/GEN 64-CSPBGA |
| AD9910BSVZ-REEL | IC DDS 1GSPS 14BIT PAR 100TQFP |
| AD9911BCPZ-REEL7 | IC DDS 500MSPS DAC 10BIT 56LFCSP |
| AD9912ABCPZ | IC DDS 1GSPS DAC 14BIT 64LFCSP |
| AD9913BCPZ-REEL7 | IC DDS 250MSPS 10BIT ADC 32LFCSP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9888KSZ-170 | 制造商:Analog Devices 功能描述:TV / Video IC |
| AD9888KSZ-205 | 制造商:Analog Devices 功能描述:205MHZ ANALOG GRAPHICS INTERFACE 制造商:Analog Devices 功能描述:IC ANALOG INTERFACE |
| AD9888KSZ-205KL1 | 制造商:Analog Devices 功能描述:- Rail/Tube |
| AD9889 | 制造商:Analog Devices 功能描述:- Bulk |
| AD9889A | 制造商:AD 制造商全称:Analog Devices 功能描述:High Performance HDMI/DVI Transmitter |
发布紧急采购，3分钟左右您将得到回复。