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参数资料
| 型号： | AD9888KSZ-170 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/36页 |
| 文件大小： | 0K |
| 描述： | IC ANALOG INTRFC 170MSPS 128MQFP |
| 标准包装： | 1 |
| 应用： | 图形卡，VGA 接口 |
| 接口： | 2 线串口 |
| 电源电压： | 3 V ~ 3.6 V |
| 封装/外壳： | 128-BFQFP |
| 供应商设备封装： | 128-MQFP（14x20） |
| 包装： | 托盘 |
| 安装类型： | 表面贴装 |
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AD9888
Data Sheet
Rev. C | Page 16 of 36
The 5-bit phase adjust register. The phase of the generated
sampling clock may be shifted to locate an optimum sampling
point within a clock cycle. The phase adjust register provides
32 phase-shift steps of 11.25° each. The HSYNC signal with
an identical phase shift is available through the HSOUT pin.
Phase adjustment is still available if the pixel clock is being
provided externally. The COAST pin is used to allow the
PLL to continue to run at the same frequency in the absence
of the incoming HSYNC signal. This can be used during the
vertical sync period, or any other time that the HSYNC signal
is unavailable. The polarity of the COAST signal can be set
through the coast polarity register, and the polarity of the
HSYNC signal can be set through the HSYNC polarity
register.
ALTERNATE PIXEL SAMPLING MODE
A Logic 1 input on the clock invert pin (CKINV, Pin 29) inverts
the nominal ADC clock. CKINV can be switched between frames
to implement the alternate pixel sampling mode. This allows
higher effective image resolution to be achieved at lower pixel
rates, but with lower frame rates.
On one frame, only even pixels are digitized. On the subsequent
frame, odd pixels are sampled. By reconstructing the entire frame
in the graphics controller, a complete image can be reconstructed.
This is similar to the interlacing process employed in broadcast
television systems, but the interlacing is vertical instead of
horizontal. The frame data is still presented to the display at the
full desired refresh rate (usually 60 Hz), so there are no flicker
artifacts added.
OEOEOEOEOEOE
0
244
2-
00
9
Figure 10. Odd and Even Pixels in a Frame
E2
O2
024
42
-0
1
Figure 11. Even Pixels from Frame 2
O1
E1
O1
024
42
-0
10
Figure 12. Odd Pixels from Frame 1
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
02
44
2-
0
12
Figure 13. Combined Frame Output from Graphics
O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2
0
2442
-013
Figure 14. Subsequent Frame from Controller
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9888KSZ-170 | 制造商:Analog Devices 功能描述:TV / Video IC |
| AD9888KSZ-205 | 制造商:Analog Devices 功能描述:205MHZ ANALOG GRAPHICS INTERFACE 制造商:Analog Devices 功能描述:IC ANALOG INTERFACE |
| AD9888KSZ-205KL1 | 制造商:Analog Devices 功能描述:- Rail/Tube |
| AD9889 | 制造商:Analog Devices 功能描述:- Bulk |
| AD9889A | 制造商:AD 制造商全称:Analog Devices 功能描述:High Performance HDMI/DVI Transmitter |
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