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| 型号： | AD9959BCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 10/44页 |
| 文件大小： | 0K |
| 描述： | IC DDS QUAD 10BIT DAC 56LFCSP |
| 产品培训模块： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 设计资源： | Phase Coherent FSK Modulator (CN0186) |
| 标准包装： | 1 |
| 分辨率（位）： | 10 b |
| 主 fclk： | 500MHz |
| 调节字宽（位）： | 32 b |
| 电源电压： | 1.71 V ~ 1.96 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 56-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 56-LFCSP-VQ（8x8） |
| 包装： | 托盘 |
| 产品目录页面： | 552 (CN2011-ZH PDF) |
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AD9959
Rev. B | Page 18 of 44
THEORY OF OPERATION
DDS CORE
The AD9959 has four DDS cores, each consisting of a 32-bit
phase accumulator and phase-to-amplitude converter. Together,
these digital blocks generate a digital sine wave when the phase
accumulator is clocked and the phase increment value (frequency
tuning word) is greater than 0. The phase-to-amplitude converter
simultaneously translates phase information to amplitude
information by a cos(θ) operation.
The output frequency (fOUT) of each DDS channel is a function
of the rollover rate of each phase accumulator. The exact
relationship is given in the following equation:
32
2
)
)(
(
S
OUT
f
FTW
f
=
where:
fS is the system clock rate.
FTW is the frequency tuning word and is 0 ≤ FTW ≤ 231.
232 represents the phase accumulator capacity.
Because all four channels share a common system clock, they
are inherently synchronized.
The DDS core architecture also supports the capability to phase
offset the output signal, which is performed by the channel
phase offset word (CPOW). The CPOW is a 14-bit register that
stores a phase offset value. This value is added to the output of
the phase accumulator to offset the current phase of the output
signal. Each channel has its own phase offset word register. This
feature can be used for placing all channels in a known phase
relationship relative to one another. The exact value of phase
offset is given by the following equation:
°
×
=
Φ
360
2
14
POW
DIGITAL-TO-ANALOG CONVERTER
The AD9959 incorporates four 10-bit current output DACs.
The DAC converts a digital code (amplitude) into a discrete
analog quantity. The DAC current outputs can be modeled as a
current source with high output impedance (typically 100 kΩ).
Unlike many DACs, these current outputs require termination
into AVDD via a resistor or a center-tapped transformer for
expected current flow.
Each DAC has complementary outputs that provide a combined
full-scale output current (IOUT + IOUT). The outputs always sink
current, and their sum equals the full-scale current at any point
in time. The full-scale current is controlled by means of an
external resistor (RSET) and the scalable DAC current control
bits discussed in the Modes of Operation section. The resistor,
RSET, is connected between the DAC_RSET pin and analog
ground (AGND). The full-scale current is inversely proportional
to the resistor value as follows:
(max)
91
.
18
OUT
SET
I
R
=
The maximum full-scale output current of the combined DAC
outputs is 15 mA, but limiting the output to 10 mA provides
optimal spurious-free dynamic range (SFDR) performance.
The DAC output voltage compliance range is AVDD + 0.5 V to
AVDD 0.5 V. Voltages developed beyond this range may cause
excessive harmonic distortion. Proper attention should be paid
to the load termination to keep the output voltage within its
compliance range. Exceeding this range could potentially dam-
age the DAC output circuitry.
05
24
6-
01
6
DAC
LPF
CHx_IOUT
AVDD
1:1
50
CHx_IOUT
Figure 32. Typical DAC Output Termination Configuration
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9959BCPZ1 | 制造商:AD 制造商全称:Analog Devices 功能描述:4-Channel, 500 MSPS DDS with 10-Bit DACs |
| AD9959BCPZ-REEL7 | 功能描述:IC DDS QUAD 10BIT DAC 56LFCSP RoHS:是 类别:集成电路 (IC) >> 接口 - 直接数字合成 (DDS) 系列:- 产品变化通告:Product Discontinuance 27/Oct/2011 标准包装:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 调节字宽（位）:32 b 电源电压:2.97 V ~ 5.5 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR) |
| AD9959BCPZ-REEL71 | 制造商:AD 制造商全称:Analog Devices 功能描述:4-Channel, 500 MSPS DDS with 10-Bit DACs |
| AD995PCBZ | 制造商:AD 制造商全称:Analog Devices 功能描述:1 GSPS Quadrature Digital Upconverter w/18-Bit IQ Data Path and 14-Bit DAC |
| AD9960BSTZ | 功能描述:RFID应答器 MxFE for RFID Reader Transceiver RoHS:否 制造商:Murata 存储容量:512 bit 工作温度范围:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
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