AD9979BCPZ (Analog) PDF资料下载 Datasheet(26/56 页)

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参数资料

型号：	AD9979BCPZ
厂商：	Analog Devices Inc
文件页数：	26/56页
文件大小：	0K
描述：	IC PROCESSOR CCD 14BIT 48-LFCSP
标准包装：	1
类型：	CCD 信号处理器，14 位
输入类型：	逻辑
输出类型：	逻辑
接口：	3 线串口
电流 - 电源：	48mA
安装类型：	表面贴装
封装/外壳：	48-VFQFN 裸露焊盘，CSP
供应商设备封装：	48-LFCSP-VQ（7x7）
包装：	托盘

AD9979

Rev. C | Page 32 of 56

Input Configurations

The CDS circuit samples each CCD pixel twice to extract the

video information and to reject the low frequency noise (see

Figure 43). There are three possible configurations for the CDS:

inverting CDS mode, noninverting CDS mode, and SHA mode.

CDSMODE (Address 0x00[9:8]) selects which configuration is

used (see Table 24).

SHA1

SHA2

SHD

SHP

DIFF

AMP

CDS OUTPUT

CCDINP

CCDINM

-04

Figure 43. CDS Block Diagram (Conceptual)

Inverting CDS Mode

For this configuration, the signal from the CCD is applied

to the positive input of the CDS system (CCDINP) and the

negative side (CCDINM) is grounded (see Figure 44). The

CDSMODE setting for this configuration is 0x00. Traditional

CCD applications use this configuration with the reset level

established below the AVDD supply level, by the AD9979 dc

restore circuit, at approximately 1.5 V. The maximum saturation

level is 1.0 V below the reset level, as shown in Figure 45 and

Table 18. A maximum saturation voltage of 1.4 V is also

possible when using the minimum CDS gain setting.

IMAGE

SENSOR

SHA/

CDS

CCDINM

CCDINP

AD9979

NOTES

1. COUPLING CAPACITOR IS NOT REQUIRED FOR CERTAIN

BLACK-LEVEL REFERENCE VOLTAGES.

Figure 44. Single-Input CDS Configuration

(N) SIGNAL SAMPLE

(N) RESET SAMPLE

(N + 1) RESET SAMPLE

VDD

RESET LEVEL

(VRST)

SIGNAL LEVEL

(VFS)

05957-

047

Figure 45. Traditional Inverting CDS Signal

Table 18. Inverting Voltage Levels

Signal Level

Symbol

Min

Typ

Max

Unit

Saturation

VFS

1000

1400

Reset

VRST

VDD 500

VDD 300

VDD

Supply Voltage

VDD

1600

1800

2000

Noninverting CDS Mode

If the noninverting input is desired, the reset level signal (or black

level signal) is established at a voltage above ground potential.

Saturation level (or white level) is approximately 1 V. Samples are

taken at each signal level (see Figure 46 and Table 19).