参数资料
型号: AD9992BBCZRL
厂商: Analog Devices Inc
文件页数: 20/92页
文件大小: 0K
描述: IC CCD SGNL PROC 12BIT 105CSPBGA
产品变化通告: AD9992 Discontinuation 22/Feb/2012
标准包装: 2,000
类型: CCD 信号处理器,12 位
输入类型: 逻辑
输出类型: 逻辑
接口: 3 线串口
电流 - 电源: 27mA
安装类型: 表面贴装
封装/外壳: 105-LFBGA,CSPBGA
供应商设备封装: 105-CSPBGA(8x8)
包装: 带卷 (TR)
AD9992
Rev. C | Page 27 of 92
REGION 0: USE V-SEQUENCE 3
REGION 1: USE V-SEQUENCE 2
REGION 2: USE V-SEQUENCE 1
REGION 0: USE V-SEQUENCE 3
REGION 1: USE V-SEQUENCE 2
REGION 2: USE V-SEQUENCE 1
REGION 0: USE V-SEQUENCE 2
REGION 1: USE V-SEQUENCE 0
REGION 3: USE V-SEQUENCE 0
REGION 4: USE V-SEQUENCE 2
FIELD 0
FIELD1
FIELD2
REGION 2: USE V-SEQUENCE 3
FIELD0
FIELD1
FIELD2
FIELD3
FIELD4
FIELD5
FIELD1
FIELD4
FIELD2
VPAT0
VPAT1
XV1
XV2
XV23
XV24
XV3
XV1
XV2
XV23
XV24
XV3
1
2
3
4
CREATE THE VERTICAL PATTERN GROUPS,
UP TO FOUR TOGGLE POSITIONS FOR EACH OUTPUT.
BUILD THE V-SEQUENCES BY ADDING START POLARITY,
LINE START POSITION, NUMBER OF REPEATS, ALTERNATION,
GROUP A/B/C/D INFORMATION, AND HBLK/CLPOB PULSES.
V-SEQUENCE 0
(VPAT0, 1 REP)
V-SEQUENCE 1
(VPAT1, 2 REP)
V-SEQUENCE 2
(VPAT1, N REP)
BUILD EACH FIELD BY DIVIDING INTO DIFFERENT REGIONS
AND ASSIGNING A DIFFERENT V-SEQUENCE TO EACH
(MAXIMUM OF NINE REGIONS IN EACH FIELD).
USE THE MODE REGISTERS TO CONTROL WHICH FIELDS
ARE USED, AND IN WHAT ORDER (MAXIMUM OF SEVEN
FIELDS CAN BE COMBINED IN ANY ORDER).
05
89
1-
03
3
XV1
XV2
XV23
XV24
XV3
XV1
XV2
XV23
XV24
XV3
XV1
XV2
XV23
XV24
XV3
Figure 33. Summary of Vertical Timing Generation
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