参数资料
型号: AD9992BBCZRL
厂商: Analog Devices Inc
文件页数: 32/92页
文件大小: 0K
描述: IC CCD SGNL PROC 12BIT 105CSPBGA
产品变化通告: AD9992 Discontinuation 22/Feb/2012
标准包装: 2,000
类型: CCD 信号处理器,12 位
输入类型: 逻辑
输出类型: 逻辑
接口: 3 线串口
电流 - 电源: 27mA
安装类型: 表面贴装
封装/外壳: 105-LFBGA,CSPBGA
供应商设备封装: 105-CSPBGA(8x8)
包装: 带卷 (TR)
AD9992
Rev. C | Page 38 of 92
Special Pattern Insertion
Additional flexibility is available using the SPC_PAT_EN registers,
which allows a Group B, Group C, or Group D pattern to be
inserted into a series of Group A repetitions. This feature is
useful when a different pattern is needed at the start, end, or
middle of a sequence.
Figure 46 shows an example of a sweep region using VPATA
with multiple repetitions where a single repetition of VPATB has
been added into the middle of the sequence. Figure 47 shows more
detail on how to set the registers to achieve the desired timing.
Note that VREPB is used to specify which repetition number
has the special pattern inserted instead of VPATA. VPATB
always has priority over VPATC or VPATD if more than one
SPC_PAT_EN bit is enabled (SPC_PAT_EN [0] has priority).
VD
XV1 TO XV24
HD
REGION 1: SWEEP REGION
LINE 0
LINE 1
REGION 0
REGION 2
LINE 24
LINE 25
LINE 2
SCP1
SCP2
PATTERN B INSERTED DURING PATTERN A REPETITIONS
0
58
91
-0
46
Figure 46. Example of Special Pattern Insertion
XV1
HD
V-PATTERN A
V-PATTERN B
V-PATTERN A
REP 1
REP 2
REP N
REP 5
REP 4
REP 3
REGISTER SETTINGS:
DESCRIPTION:
SPC_PAT_EN[0] = 1
V-PATTERN B IS USED AS SPECIAL PATTERN
VREPA = N
TOTAL NUMBER OF REPS USED FOR SEQUENCE (N REPS)
VREPB = 4
REP 4 USES V-PATTERN B INSTEAD OF V-PATTERN A
NOTES
1. VSTARTB MUST BE SET EQUAL TO VSTARTA.
05
89
1-
0
47
Figure 47. Example of Special Pattern Insertion, Detail
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