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| 型号： | AD9992BBCZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 29/92页 |
| 文件大小： | 0K |
| 描述： | IC CCD SGNL PROC 12BIT 105CSPBGA |
| 产品变化通告： | AD9992 Discontinuation 22/Feb/2012 |
| 标准包装： | 2,000 |
| 类型： | CCD 信号处理器，12 位 |
| 输入类型： | 逻辑 |
| 输出类型： | 逻辑 |
| 接口： | 3 线串口 |
| 电流 - 电源： | 27mA |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 105-LFBGA，CSPBGA |
| 供应商设备封装： | 105-CSPBGA（8x8） |
| 包装： | 带卷 (TR) |
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AD9992
Rev. C | Page 35 of 92
Using the LASTREPLEN_EN
The LASTREPLEN_EN register (Address 0x00, Bits [19:16] in
the sequence registers) is used to enable a separate pattern
length to be used in the final repetition of several pulse
repetitions. It is recommended that the LASTREPLEN_EN
register bits be set high (enabled) and the LASTREPLEN_A,
LASTREPLEN_B, LASTREPLEN_C, and LASTREPLEN_D
registers be set to a value equal to the VLENA, VLENB,
VLENC, and VLEND register values, respectively.
Generating Line Alternation for V-Sequences and HBLK
During low resolution readout, some CCDs require a different
number of vertical clocks on alternate lines. The AD9992 can
support this by using the VREP registers. This allows a different
number of V-pattern group repetitions to be programmed on
odd and even lines. Only the number of repeats can be different
in odd and even lines, while the V-pattern group remains the same.
There are separate controls for the assigned Group A, Group B,
Group C, and Group D patterns. All groups can support odd and
even line alternation. Group A uses the VREPA_1 register and
the VREPA_2 register; Group B, Group C, and Group D use
the corresponding VREP_ODD register and VREP_EVEN
register. With the additional VREPA_3 register and VREPA_4
register, Group A can also support 3-line and 4-line alternation.
As discussed in the Generating HBLK Line Alternation section,
the HBLK signal can be alternated for odd and even lines. Figure
shows an example of V-pattern group repetition alternation
and HBLK Mode 0 alternation used together.
XV1
XV2
XV24
HD
HBLK
XVTOGE1
XVTOGE2
XVTOGO1
XVTOGO2
XVTOGE1
XVTOGE2
NOTES
1. THE NUMBER OF REPEATS FOR V-PATTERN GROUPS A/B/C/D CAN BE ALTERNATED ON ODD AND EVEN LINES.
2. GROUP A ALSO SUPPORTS 3- AND 4-LINE ALTERNATION USING THE ADDITIONAL VREPA_3 AND VREPA_4 REGISTERS.
3. THE HBLK TOGGLE POSITIONS CAN BE ALTERNATED BETWEEN ODD AND EVEN LINES TO GENERATE DIFFERENT HBLK PATTERNS.
VREPA_1 = 2
(OR VREPB/C/D_EVEN = 2)
VREPA_2 = 5
(OR VREPB/C/D_ODD = 5)
VREPA_1 = 2
(OR VREPB/C/D_EVEN = 2)
05
89
1-
04
2
Figure 42. Odd/Even Line Alternation of V-Pattern Group Repetitions and HBLK Toggle Positions
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| AD9993BBCZ | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包装:托盘 零件状态:在售 类型:ADC，DAC 输入类型:LVDS 输出类型:LVDS 接口:SPI 电流 - 电源:- 工作温度:- 安装类型:表面贴装 封装/外壳:196-LFBGA，CSPBGA 供应商器件封装:196-CSPBGA（12x12） 标准包装:1 |
| AD9993BBCZRL | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包装:带卷（TR） 零件状态:在售 类型:ADC，DAC 输入类型:LVDS 输出类型:LVDS 接口:SPI 电流 - 电源:- 工作温度:- 安装类型:表面贴装 封装/外壳:196-LFBGA，CSPBGA 供应商器件封装:196-CSPBGA（12x12） 标准包装:1,500 |
| AD9993-EBZ | 功能描述:EVAL BOARD MXFE AD9993 制造商:analog devices inc. 系列:* 零件状态:在售 标准包装:1 |
| AD9994 | 制造商:AD 制造商全称:Analog Devices 功能描述:12-Bit CCD Signal Processor with Precision Timing Generator |
| AD9994BCP | 制造商:Analog Devices 功能描述:AFE GEN PURPOSE 12-BIT 64LFCSP - Bulk |
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