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参数资料
| 型号： | ADAV801ASTZ-REEL |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 消费家电 |
| 英文描述： | Audio Codec for Recordable DVD |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO64 |
| 封装： | ROHS COMPLIANT, MS-026BCD, LQFP-64 |
| 文件页数： | 15/56页 |
| 文件大小： | 1405K |
| 代理商： | ADAV801ASTZ-REEL |
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ADAV801
FUNCTIONAL DESCRIP
ADC SECTION
The ADAV801’s ADC section is implemented using a second-
order multibit (5 bits)
Σ
-
modulator. The modulator is
sampled at either half of the ADC MCLK rate (modulator clo
= 128 × f
S
) or one-quarter of the ADC MCLK rate (modulator
clock = 64 × f
S
). The digital decimator consists of a Sinc^5 filter
followed by a cascade of three half-band FIR filters. The Sin
decimates by a factor of 16 at 48 kHz
96 kHz. Each of the half-band filters decimates by a factor of 2.
Figure 23 shows the details of the ADC section. The ADC can
be clocked by a number of different clock sources to control t
sample rate. MCLK selection for the ADC is set by Internal
Clocking Control Register 1 (Address 0x76). The ADC provide
an output word of up to 24 bits in resolution in twos comple-
ment format. The output word can be routed to ei
output ports, the sample rate converter, or the SPDIF digital
transmitter.
D
S
)
Rev. 0 | Page 15 of 56
TION
ck
c
and by a factor of 8 at
he
s
ther the
P
P
M
X
REG 0x76
BITS 4–2
REG 0x6F
BITS 1–0
0
D
S
)
ADC MCLK
DIVIDER
ADC
MCLK
ADC
Figure 23. Clock Path Control on the ADC
Programmable Gain Amplifier (PGA)
The input of the record channel features a PGA that converts
the single-ended signal to a differential signal, which is applied
to the analog Σ-Δ modulator of the ADC. The PGA can be
programmed to amplify a signal by up to 24 dB in 0.5 dB
increments. Figure 24 shows the structure of the PGA circuit.
4k
TO 64k
125
CAPxN
EXTERNAL
CAPACITOR
(1nF NPO)
VREF
TO
MODULATOR
EXTERNAL
CAPACITOR
(1nF NPO)
CAPxP
EXTERNAL
CAPACITOR
(1nF NPO)
8k
8k
0
4k
125
Figure 24. PGA Block Diagram
Analog Σ- Modulator
The ADC features a second-order, multibit, Σ-Δ modulator. The
input features two integrators in cascade followed by a flash
converter. This multibit output is directed to a scrambler,
followed by a DAC for loop feedback. The flash ADC outp
also converted from thermometer coding to binary codin
input as a 5-bit word to the decimator. F
ADC block diagram.
ut is
g for
igure 25 shows the
The ADC also features independent digital volume control for
the left and right channels. The volume control consists of
256 linear steps, with each step reducing the digital output
codes by 0.39%. Each channel also has a peak detector that
records the peak level of the input signal. The peak detector
register is cleared by reading it.
ADC MCLK
AMC
(REG 0X63
BIT-7)
MULTIBIT
Σ
–
MODULATOR
DECIMATOR
HPF
PEAK
DETECT
VOLUME
ONTROL
C
0
SINC^5
HALF-BAND
FILTER
MODULATOR
CLOCK
(6.144MHz MAX)
384kHz
768kHz
SINC
COMPENSATION
192kHz
384kHz
HALF-BAND
FILTER
96kHz
192kHz
48kHz
96kHz
÷
2
÷
4
Diagram
Figure 25. A
DC Block
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADAV802AST | 制造商:Analog Devices 功能描述:AUDIO CODEC FOR RECORDABLE DVD - Bulk |
| ADAV802ASTZ | 制造商:Analog Devices 功能描述: |
| ADAV803 | 制造商:AD 制造商全称:Analog Devices 功能描述:Audio Codec for Recordable DVD |
| ADAV803AST | 制造商:Analog Devices 功能描述:AUDIO CODEC FOR RECORDABLE DVD - Bulk |
| ADAV803ASTZ | 功能描述:IC CODEC AUDIO R-DVD 3.3V 64LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 编解码器 系列:- 标准包装:2,500 系列:- 类型:立体声音频 数据接口:串行 分辨率（位）:18 b ADC / DAC 数量:2 / 2 三角积分调变:是 S/N 比，标准 ADC / DAC (db):81.5 / 88 动态范围，标准 ADC / DAC (db):82 / 87.5 电压 - 电源，模拟:2.6 V ~ 3.3 V 电压 - 电源，数字:1.7 V ~ 3.3 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-WFQFN 裸露焊盘 供应商设备封装:48-TQFN-EP（7x7） 包装:带卷 (TR) |
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