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参数资料
| 型号： | ADAV801ASTZ-REEL |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 消费家电 |
| 英文描述： | Audio Codec for Recordable DVD |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO64 |
| 封装： | ROHS COMPLIANT, MS-026BCD, LQFP-64 |
| 文件页数： | 28/56页 |
| 文件大小： | 1405K |
| 代理商： | ADAV801ASTZ-REEL |
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ADAV801
Rev. 0 | Page 28 of 56
0
REG 0x76
BITS 4–2
DIR PLL (512 ×
f
S
)
DIR PLL (256 ×
f
S
)
PLLINT1
PLLINT2
MCLKI
XIN
ICLK1
ICLK2
PLL CLOCK
REG 0x06
BITS 4–3
MCLK
ADC
OUTPUT
PORT
OLRCLK
OBC
OSDATA
LK
REG 0x76
BITS 7–5
DIR PLL (512 ×
f
S
)
DIR PLL (256 ×
f
S
)
PLLINT1
PLLINT2
MCLKI
XIN
ICLK1
ICLK2
PLL CLOCK
REG 0x04
BITS 4-3
MCLK
DAC
INPUT
PORT
ILRCLK
IBCLK
ISDATA
REG 0x77
BITS 4–3
REG 0x00
BITS 3–2
DIVIDER
REG 0x00
BITS 1–0
ICLK1
REG 0x00
BITS 4–5
REG 0x76
BITS 1–0
MCLKI
XIN
PLLINT1
PLLINT2
ICLK2
DIR PLL (512 ×
f
S
)
DIR PLL (256 ×
f
S
)
REG 0x00
BITS 1-0
MCLKI
XIN
PLLINT1
PLLINT2
DIVIDER
DIVIDER
SRC
MCLK
Figure 50. SPORT Clocking Scheme
le,
MCLKI input to ensure that the
synchronized.
C and serial port are
The SPORTs can be set
justified or right-justified formats with different word lengths
by programming the appropriate bits in the playback register,
auxiliary input port register, record register, and auxiliary
output port-control register. Figure 51 is a timing diagram of
the serial data port formats.
Clocking Scheme
The ADAV801 provides a flexible choice of on-chip and off-
chip clocking sources. The on-chip oscillator with dual PLLs is
intended to offer complete system clocking requirements for
use with available MPEG encoders, decoders, or a combination
of codecs. The oscillator function is designed for generation of a
27 MHz video clock from a 27 MHz crystal connected between
the XIN and XOUT pins. Capacitors must also be connected
between these pins and DGND, as shown in Figure 35. The
capacitor values should be specified by the crystal manufacturer.
A square wave version of the crystal clock is output on the
MCLKO pin. If the system has a 27 MHz clock available, this
clock can be connected directly to the XIN pin.
ive data in I
2
S, left-
Care should be taken to ensure that the clock rate is appropriate
for whatever block is connected to the serial port. For examp
if the ADC is running from the MCLKI input at 256 × f
S
, then
the master clock for the SPORT should also run from the
AD
to transmit or rece
0
LRCLK
BCLK
SDATA
LRCLK
BCLK
SDATA
LRCLK
BCLK
SDATA
LSB
LSB
LSB
LSB
LSB
LSB
LEFT CHANNEL
RIGHT CHANNEL
RIGHT CHANNEL
LEFT CHANNEL
LEFT CHANNEL
RIGHT CHANNEL
MSB
MSB
MSB
MSB
MSB
MSB
RIGHT-JUSTIFIED MODE — SELECT NUMBER OF BITS PER CHANNEL
I
2
S MODE — 16 BITS TO 24 BITS PER CHANNEL
LEFT-JUSTIFIED MODE — 16 BITS TO 24 BITS PER CHANNEL
Figure 51. Serial Data Modes
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADAV802AST | 制造商:Analog Devices 功能描述:AUDIO CODEC FOR RECORDABLE DVD - Bulk |
| ADAV802ASTZ | 制造商:Analog Devices 功能描述: |
| ADAV803 | 制造商:AD 制造商全称:Analog Devices 功能描述:Audio Codec for Recordable DVD |
| ADAV803AST | 制造商:Analog Devices 功能描述:AUDIO CODEC FOR RECORDABLE DVD - Bulk |
| ADAV803ASTZ | 功能描述:IC CODEC AUDIO R-DVD 3.3V 64LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 编解码器 系列:- 标准包装:2,500 系列:- 类型:立体声音频 数据接口:串行 分辨率（位）:18 b ADC / DAC 数量:2 / 2 三角积分调变:是 S/N 比，标准 ADC / DAC (db):81.5 / 88 动态范围，标准 ADC / DAC (db):82 / 87.5 电压 - 电源，模拟:2.6 V ~ 3.3 V 电压 - 电源，数字:1.7 V ~ 3.3 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-WFQFN 裸露焊盘 供应商设备封装:48-TQFN-EP（7x7） 包装:带卷 (TR) |
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