参数资料
型号: ADAV801ASTZ-REEL
厂商: ANALOG DEVICES INC
元件分类: 消费家电
英文描述: Audio Codec for Recordable DVD
中文描述: SPECIALTY CONSUMER CIRCUIT, PDSO64
封装: ROHS COMPLIANT, MS-026BCD, LQFP-64
文件页数: 9/56页
文件大小: 1405K
代理商: ADAV801ASTZ-REEL
ADAV801
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. 0 | Page 9 of 56
N
V
N
V
O
I
I
I
ZEROL/INT
ZEROR
DVDD
DGND
ADVDD
ADGND
PLL_LF2
PLL_LF1
PLL_GND
PLL_VDD
DGND
SYSCLK1
SYSCLK2
SYSCLK3
XIN
XOUT
MCLKO
MCLKI
DVDD
DGND
39
38
37
41
40
36
35
34
33
42
43
44
45
46
47
48
17 18 19 20 21 22 23 24
I
I
I
O
O
O
D
O
O
D
O
O
1
2
3
4
5
6
7
8
9
10
11
12
64 63 62 61 60 59 58
C
C
A
C
C
A
A
V
A
F
A
A
VINR
VINL
AGND
AVDD
DIR_LF
DIR_GND
DIR_VDD
RESET
CLATCH
CIN
CCLK
COUT
13
14
15
16
25 26 27
31
30
29
28
32
57 56 55 54 53 52 51 50 49
ADAV801
TOP VIEW
(Not to Scale)
0
PIN 1
NC = NO CONNECT
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
1
VINR
2
VINL
3
AGND
4
AVDD
5
DIR_LF
6
DIR_GND
7
DIR_VDD
8
RESET
9
CLATCH
10
CIN
11
CCLK
12
COUT
13
ZEROL/INT
I/O
I
I
I
I
I
I
O
O
Description
Analog Audio Input, Right Channel.
Analog Audio Input, Left Channel.
Analog Ground.
Analog Voltage Supply.
DIR Phase-Locked Loop (PLL) Filter Pin.
Supply Ground for DIR Analog Section. This pin should be connected to AGND.
Supply for DIR Analog Section. This pin should be connected to AVDD.
Asychronous Reset Input (Active Low).
Chip Select (Control Latch) Pin of SPI-Compatible Control Interface.
Data Input of SPI-Compatible Control Interface.
Clock Input of SPI-Compatible Control Interface.
Data Output of SPI-Compatible Control Interface.
Left Channel (Output) Zero Flag or Interrupt (Output) Flag. The function of this pin is determined
by the INTRPT pin in DAC Control Register 4.
Right Channel (Output) Zero Flag.
Digital Voltage Supply.
Digital Ground.
Sampling Clock (LRCLK) of Playback Digital Input Port.
Serial Clock (BCLK) of Playback Digital Input Port.
Data Input of Playback Digital Input Port.
Sampling Clock (LRCLK) of Record Digital Output Port.
Serial Clock (BCLK) of Record Digital Output Port.
Data Output of Record Digital Output Port.
Input to Digital Input Receiver (S/PDIF).
Interface Digital Voltage Supply.
Interface Digital Ground.
S/PDIF Output from DIT.
Sampling Clock (LRCLK) of Auxiliary Digital Output Port.
14
15
16
17
18
19
20
21
22
23
24
25
26
27
ZEROR
DVDD
DGND
ILRCLK
IBCLK
ISDATA
OLRCLK
OBCLK
OSDATA
DIRIN
ODVDD
ODGND
DITOUT
OAUXLRCLK
O
I/O
I/O
I
I/O
I/O
O
I
O
I/O
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