参数资料
型号: ADAV801ASTZ
厂商: Analog Devices Inc
文件页数: 11/60页
文件大小: 0K
描述: IC CODEC AUDIO R-DVD 3.3V 64LQFP
标准包装: 1
类型: 音频编解码器
数据接口: 串行
分辨率(位): 24 b
ADC / DAC 数量: 2 / 2
三角积分调变:
动态范围,标准 ADC / DAC (db): 102 / 101
电压 - 电源,模拟: 3 V ~ 3.6 V
电压 - 电源,数字: 3 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 托盘
配用: EVAL-ADAV801EBZ-ND - BOARD EVALUATION FOR ADAV801
ADAV801
Rev. A | Page 19 of 60
SAMPLE RATE CONVERTER (SRC) FUNCTIONAL
OVERVIEW
During asynchronous sample rate conversion, data can be
converted at the same sample rate or at different sample rates.
The simplest approach to an asynchronous sample rate
conversion is to use a zero-order hold between the two
samplers, as shown in Figure 29. In an asynchronous system, T2
is never equal to T1, nor is the ratio between T2 and T1
rational. As a result, samples at fS_OUT are repeated or dropped,
producing an error in the resampling process.
The frequency domain shows the wide side lobes that result
from this error when the sampling of fS_OUT is convolved with
the attenuated images from the sin(x)/x nature of the zero-order
hold. The images at fS_IN (dc signal images) of the zero-order
hold are infinitely attenuated. Because the ratio of T2 to T1 is an
irrational number, the error resulting from the resampling at
fS_OUT can never be eliminated. The error can be significantly
reduced, however, through interpolation of the input data at
fS_IN. Therefore, the sample rate converter in the ADAV801 is
conceptually interpolated by a factor of 220.
04
57
7-
0
09
ZERO-ORDER
HOLD
fS_IN = 1/T1
fS_OUT = 1/T2
OUT
IN
ORIGINAL SIGNAL
SAMPLED AT
fS_IN
SIN(X)/X OF ZERO-ORDER HOLD
SPECTRUM OF ZERO-ORDER HOLD OUTPUT
SPECTRUM OF
fS_OUT SAMPLING
fS_OUT
2 ×
fS_OUT
FREQUENCY RESPONSE OF
fS_OUT CONVOLVED
WITH ZERO-ORDER HOLD SPECTRUM
Figure 29. Zero-Order Hold Used by fS_ OUT to Resample Data from fS_IN
Conceptual High Interpolation Model
Interpolation of the input data by a factor of 220 involves placing
(220 1) samples between each fS_IN sample. Figure 30 shows
both the time domain and the frequency domain of interpolation
by a factor of 220. Conceptually, interpolation by 220 involves the
steps of zero-stuffing (220 1) number of samples between each
fS_IN sample and convolving this interpolated signal with a
digital low-pass filter to suppress the images. In the time
domain, it can be seen that fS_OUT selects the closest fS_IN × 220
sample from the zero-order hold, as opposed to the nearest fS_IN
sample in the case of no interpolation. This significantly
reduces the resampling error.
04
57
7-
01
0
fS_IN
fS_OUT
OUT
IN
INTERPOLATE
BY N
LOW-PASS
FILTER
ZERO-ORDER
HOLD
TIME DOMAIN OF
fS_IN SAMPLES
TIME DOMAIN OUTPUT OF THE LOW-PASS FILTER
TIME DOMAIN OF
fS_OUT RESAMPLING
TIME DOMAIN OF THE ZERO-ORDER HOLD OUTPUT
Figure 30. SRC Time Domain
In the frequency domain shown in Figure 31, the interpolation
expands the frequency axis of the zero-order hold. The images
from the interpolation can be sufficiently attenuated by a good
low-pass filter. The images from the zero-order hold are now
pushed by a factor of 220 closer to the infinite attenuation point
of the zero-order hold, which is fS_IN × 220. The images at the
zero-order hold are the determining factor for the fidelity of the
output at fS_OUT.
04
57
7-
01
1
fS_IN
220 ×
fS_IN
220 ×
fS_IN
220 ×
fS_IN
fS_OUT
OUT
IN
INTERPOLATE
BY N
LOW-PASS
FILTER
ZERO-ORDER
HOLD
FREQUENCY DOMAIN OF SAMPLES AT
fS_IN
FREQUENCY DOMAIN OF THE INTERPOLATION
FREQUENCY DOMAIN OF
fS_OUT RESAMPLING
FREQUENCY DOMAIN
AFTER RESAMPLING
SIN(X)/X OF ZERO-ORDER HOLD
Figure 31. Frequency Domain of the Interpolation and Resampling
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ADAV801ASTZ-REEL 功能描述:IC CODEC AUDIO R-DVD 3.3V 64LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 编解码器 系列:- 标准包装:2,500 系列:- 类型:立体声音频 数据接口:串行 分辨率(位):18 b ADC / DAC 数量:2 / 2 三角积分调变:是 S/N 比,标准 ADC / DAC (db):81.5 / 88 动态范围,标准 ADC / DAC (db):82 / 87.5 电压 - 电源,模拟:2.6 V ~ 3.3 V 电压 - 电源,数字:1.7 V ~ 3.3 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-WFQFN 裸露焊盘 供应商设备封装:48-TQFN-EP(7x7) 包装:带卷 (TR)
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