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| 型号： | ADF4350BCPZ-RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 11/32页 |
| 文件大小： | 0K |
| 描述： | IC SYNTH PLL VCO FN/IN 32LFCSP |
| 产品变化通告： | ADF4350, ADF4905/6 N-counter Change 05/Mar/2012 |
| 设计资源： | Broadband Low EVM Direct Conversion Transmitter (CN0134) Broadband Low EVM Direct Conversion Transmitter Using LO Divide-by-2 Modulator (CN0144) Using low noise linear drop-out regulators to power wideband PLL & VCO IC's (CN0147) |
| 特色产品： | ADF4350: Wideband PLL Synthesizer with integrated VCO |
| 标准包装： | 1 |
| 类型： | 扇出配送，分数-N，整数-N，时钟/频率合成器（RF） |
| PLL： | 是 |
| 输入： | CMOS |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:3 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 4.4GHz |
| 除法器/乘法器： | 是/是 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-VQ（5x5） |
| 包装： | 标准包装 |
| 产品目录页面： | 551 (CN2011-ZH PDF) |
| 其它名称： | ADF4350BCPZ-RL7DKR |
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ADF4350
Rev. A | Page 19 of 32
When the doubler is enabled and the lowest spur mode is
chosen, the in-band phase noise performance is sensitive to
the REFIN duty cycle. The phase noise degradation can be as
much as 5 dB for the REFIN duty cycles outside a 45% to 55%
range. The phase noise is insensitive to the REFIN duty cycle
in the lowest noise mode and when the doubler is disabled.
The maximum allowable REFIN frequency when the doubler
is enabled is 30 MHz.
RDIV2
Setting the DB24 bit to 1 inserts a divide-by-2 toggle flip-flop
between the R counter and PFD, which extends the maximum
REFIN input rate. This function allows a 50% duty cycle signal
to appear at the PFD input, which is necessary for cycle slip
reduction.
10–Bit R Counter
The 10–bit R counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock
to the PFD. Division ratios from 1 to 1023 are allowed.
Double Buffer
DB13 enables or disables double buffering of Bits [DB22:DB20]
in Register 4. The Divider Select section explains how double
buffering works.
Charge Pump Current Setting
Bits [DB12:DB09] set the charge pump current setting. This
should be set to the charge pump current that the loop filter
is designed with (see Figure 26).
LDF
Setting DB8 to 1 enables integer–N digital lock detect,
when the FRAC part of the divider is 0; setting DB8 to 0
enables fractional–N digital lock detect.
Lock Detect Precision (LDP)
When DB7 is set to 0, 40 consecutive PFD cycles of 10 ns must
occur before digital lock detect is set. When this bit is programmed
to 1, 40 consecutive reference cycles of 6 ns must occur before
digital lock detect is set. This refers to fractional-N digital lock
detect (set DB8 to 0). With integer–N digital lock detect activated
(set DB8 to 1), and DB7 set to 0, then five consecutive cycles of
6 ns need to occur before digital lock detect is set. When DB7 is
set to 1, five consecutive cycles of 10 ns must occur.
Phase Detector Polarity
DB6 sets the phase detector polarity. When a passive loop filter,
or noninverting active loop filter is used, this should be set to 1.
If an active filter with an inverting characteristic is used, it
should be set to 0.
Power-Down
DB5 provides the programmable power-down mode. Setting this
bit to 1 performs a power-down. Setting this bit to 0 returns the
synthesizer to normal operation. When in software power-down
mode, the part retains all information in its registers. Only if the
supply voltages are removed are the register contents lost.
When a power-down is activated, the following events occur:
The synthesizer counters are forced to their load state
conditions.
The VCO is powered down.
The charge pump is forced into three-state mode.
The digital lock detect circuitry is reset.
The RFOUT buffers are disabled.
The input register remains active and capable of loading
and latching data.
Charge Pump Three-State
DB4 puts the charge pump into three-state mode when
programmed to 1. It should be set to 0 for normal operation.
Counter Reset
DB3 is the R counter and N counter reset bit for the ADF4350.
When this is 1, the RF synthesizer N counter and R counter are
held in reset. For normal operation, this bit should be set to 0.
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相关代理商/技术参数 |
参数描述 |
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| ADF4350BCPZ-U6 | 制造商:Analog Devices 功能描述: |
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| ADF4351BCPZ | 功能描述:IC SYNTH PLL VCO 32LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| ADF4351BCPZ-RL7 | 功能描述:IC SYNTH PLL VCO 32LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
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