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| 型号： | ADM1075-2ACPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 22/52页 |
| 文件大小： | 0K |
| 描述： | IC HOT SWAP CTRLR -48V 28LFCSP |
| 标准包装： | 1 |
| 类型： | 热交换控制器 |
| 应用： | -48V 远程电力系统，高可用性，电信/数据通信系统 |
| 内部开关： | 无 |
| 电流限制： | 可调 |
| 电源电压： | -35 V ~ -80 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 28-LFCSP-WQ（5x5） |
| 包装： | 托盘 |
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ADM1075
Data Sheet
V
1V
ISET
FLB
SS
Assuming V ISET equals the voltage on the ISET pin, the resistor
divider should be sized to set the ISET voltage as follows:
V ISET = (V SENSE × 50) for ADM1075-1 or
V ISET = (V SENSE × 25) for ADM1075-2
where V SENS E is the sense voltage limit. The VCAP rail can also
C SS =
CURRENT LIMIT
REFERENCE
0.1V
t
Figure 47. Interaction of Soft Start, Foldback, and ISET Current Limits
SETTING THE CURRENT LIMIT (ISET)
The maximum current limit is partially determined by selecting
a sense resistor to match the current sense voltage limit on the
controller for the desired load current. However, as currents
become larger, the sense resistor value becomes smaller and
resolution can be difficult to achieve when selecting the appropri-
ate sense resistor value. The ADM1075 provides an adjustable
sense voltage limit to deal with this issue. The device allows the
user to program the required current sense voltage limit from
15 mV to 25 mV for the ADM1075-1 and from 30 mV to 50 mV
The default value of 20 mV/40 mV is achieved by connecting
the ISET pin directly to the VCAP pin (VCAP > 1.65 V ISET
reference select threshold). This configures the device to use an
internal 1 V reference, which equates to 20 mV/40 mV at the
sense inputs (see Figure 48(a)).
VCAP VCAP
be used as the pull-up supply for setting the I 2 C address. The
VCAP pin should not be used for any other purpose. To
guarantee accuracy specifications, care must be taken to not
load the VCAP pin by more than 100 μA.
SOFT START
A capacitor connected to the SS pin determines the inrush
current profile. Before the FET is enabled, the output voltage of
the current limit reference selector block is clamped at 100 mV.
This, in turn, holds the current limit reference at approximately
2 mV for the ADM1075-1 or 4 mV for the ADM1075-2 . When
the FET is requested to turn on, the SS pin is held at ground
until the voltage between the SENSE+ and SENSE? pins
(V SENSE ) reaches the circuit breaker voltage, V CB .
V CB = V SENSECL ? V CBOS
When the load current generates a sense voltage equal to V CB , a
10 μA current source is enabled, which charges the SS capacitor
and results in a linear ramping voltage on the SS pin. The
current limit reference also ramps up accordingly, allowing the
regulated load current to ramp up, while avoiding sudden
transients during power-up. The SS capacitor value is given by
I SS × t
V ISET
where I SS = 10 μA, and t is the SS ramp time.
For example, a 10 nF capacitor gives a soft start time of 1 ms.
Note that the SS voltage may intersect with the PLIM or
foldback (FLB) voltage, and the current limit reference may
C1
C1
R1
change to follow PLIM (see Figure 47). This has minimal
ISET
ADM1075
(PARTIAL)
ISET
ADM1075
(PARTIAL)
impact on startup because the output voltage rises at a similar
rate to SS.
CONSTANT POWER FOLDBACK (PLIM)
R2
Foldback is a method that actively reduces the current limit as
the voltage drop across the FET increases. It keeps the power
across the FET below the programmed value during power-up,
VEE
VEE
overcurrent, or short-circuit events. This allows a smaller FET
to be used, resulting in significant cost savings. The foldback
(A) (B)
Figure 48. (a) Fixed 20 mV/40 mV Current Sense Limit
(b) Adjustable 15 mV to 50 mV Current Sense Limit
To set the sense voltage in the 15 mV to 50 mV range, a resistor
divider is used to apply a reference voltage to the ISET pin (see
Figure 48(b)). The VCAP pin has a 2.7 V internally generated
voltage that can be used to set a voltage at the ISET pin.
method employed is a constant power foldback scheme, meaning
power in the FET is held constant regardless of the V DS of the
FET. This simplifies the task of ensuring that the FET is always
operating within the SOA region.
The ADM1075 detects the voltage drop across the FET by
monitoring the voltage on the drain of the FET (via the PLIM
pin). The device relies on the principle that the source of the
FET is at the most negative expected supply voltage, and the
magnitude of the drain voltage is relative to that of the V DS of
the FET. Using a resistor divider from the drain of the FET to
Rev. C | Page 22 of 52
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| ADM1075-2ACPZ-RL7 | 功能描述:IC HOT SWAP CTRLR -48V 28LFCSP RoHS:是 类别:集成电路 (IC) >> PMIC - 热交换 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:119 系列:- 类型:热交换控制器 应用:通用型，PCI Express? 内部开关:无 电流限制:- 电源电压:3.3V，12V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:80-TQFP 供应商设备封装:80-TQFP（12x12） 包装:托盘 产品目录页面:1423 (CN2011-ZH PDF) |
| ADM1075-2ARUZ | 功能描述:IC CTRLR HOTSWAP -48V 28TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 热交换 系列:- 标准包装:50 系列:- 类型:热交换控制器 应用:-48V 远程电力系统，AdvancedTCA ? 系统，高可用性 内部开关:无 电流限制:可调 电源电压:11.5 V ~ 14.5 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:10-TFSOP，10-MSOP（0.118"，3.00mm 宽） 供应商设备封装:10-MSOP 包装:管件 |
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