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参数资料
| 型号： | ADMC300-ADVEVALKIT |
| 厂商： | Analog Devices, Inc. |
| 元件分类： | 圆形连接器 |
| 英文描述： | Circular Connector; No. of Contacts:13; Series:MS27497; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:10; Circular Contact Gender:Socket; Circular Shell Style:Wall Mount Receptacle RoHS Compliant: No |
| 中文描述： | 高性能基于DSP的电机控制器 |
| 文件页数： | 11/42页 |
| 文件大小： | 297K |
| 代理商： | ADMC300-ADVEVALKIT |
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ADMC300
–11–
REV. B
Table IV. ROM Utilities
Utility
Address
Function
PER_RST
UMASK
0x07E4
0x0E21
Peripheral Reset.
Limits Unsigned Value to Given
Range.
Facilitates User Setup of Vector
Table.
Limits Signed Value to Given
Range.
Cosine Function.
Sine Function.
Arctangent Function.
Reciprocal (1/x) Function.
Square Root Function.
Natural Logarithm Function.
Logarithm (Base 10) Function.
Fixed Point to Floating Point
Conversion.
Floating Point to Fixed Point
Conversion.
Floating Point Addition.
Floating Point Subtraction.
Floating Point Multiplication.
Floating Point Division.
Floating Point Multiply and
Accumulate.
Forward and Reverse Park
Transformation (Vector
Rotation).
Reverse Clark Transformation.
Forward Clark Transformation.
Unsigned Single Precision
Division (Integer).
Unsigned Single Precision
Division (Fractional).
Exit to Debugger after Running
User Program.
PUT_VECTOR
0x0E28
SMASK
0x0E35
ADMC_COS
ADMC_SIN
ARCTAN
RECIPROCAL
SQRT
LN
LOG
FLTONE
0x0E55
0x0E5C
0x0E72
0x0E94
0x0EAA
0x0EE4
0x0EE7
0x0F03
FIXONE
0x0F08
FPA
FPS
FPM
FPD
FPMACC
0x0F0C
0x0F1B
0x0F2B
0x0F34
0x0F55
PARK
0x0F77
REV_CLARK
FOR_CLARK
SDIVQINT
0x0F8B
0x0FA1
0x0FAB
SDIVQ
0x0FB4
EXIT
0x0FC6
SYSTEM INTERFACE
Figure 4 shows a basic system configuration for the ADMC300
with an external crystal and serial E
2
PROM for boot loading of
program and data memory RAM.
ADMC300
XTAL
CLKIN
DR1A
SCLK1
RFS1/
SROM
DATA
CLK
RESET
12.5 MHz
CLKOUT
RESET
SERIAL
E
PROM
20pF
20pF
Figure 4. Basic System Configuration
Clock Signals
The ADMC300 can be clocked by either a crystal or a TTL-
compatible clock signal. The CLKIN input cannot be halted,
changed during operation or operated below the specified
minimum frequency during normal operation. If an external
clock is used, it should be a TTL-compatible signal running at
half the instruction rate. The signal is connected to the CLKIN
pin of the ADMC300. In this mode, with an external clock
signal, the XTAL pin must be left unconnected. The ADMC300
uses an input clock with a frequency equal to half the instruc-
tion rate; a 12.5 MHz input clock yields a 40 ns processor cycle
(which is equivalent to 25 MHz). Normally instructions are
executed in a single processor cycle. All device timing is
relative to the internal instruction rate, which is indicated by
the CLKOUT signal.
Because the ADMC300 includes an on-chip oscillator circuit,
an external crystal may be used instead of a clock source, as
shown in Figure 4. The crystal should be connected across the
CLKIN and XTAL pins, with two capacitors as shown in
Figure 4. A parallel-resonant, fundamental frequency, micro-
processor-grade crystal should be used. A clock output signal
(CLKOUT) is generated by the processor at the processor’s
cycle rate of twice the input frequency.
Reset
The
RESET
signal initiates a master reset of the ADMC300.
The
RESET
signal must be asserted during the power-up se-
quence to assure proper initialization.
RESET
during initial
power-up must be held long enough to allow the internal clock
to stabilize. If
RESET
is activated any time after power-up, the
clock continues to run and does not require stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid V
DD
is ap-
plied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum
of 2000 CLKIN cycles ensures that the PLL has locked, but
does not include the crystal oscillator start-up time. During this
power-up sequence, the
RESET
signal should be held low. On
any subsequent resets, the
RESET
signal must meet the mini-
mum pulsewidth specification, t
RSP
.
If an RC circuit is used to generate the
RESET
signal, the use of
an external Schmitt trigger is recommended.
The master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts, initializes DSP core regis-
ters and performs a full reset of all of the motor control periph-
erals. When the
RESET
line is released, the first instruction is
fetched from internal program memory ROM at location 0x0800.
The internal monitor code at this location then commences the
boot-loading sequence over the serial port, SPORT1.
Boot Loading
On power-up or reset, the ADMC300 is configured so that
execution begins at the internal PM ROM at address 0x0800.
This starts execution of the internal monitor function that first
performs some initialization functions and copies a default inter-
rupt vector table to addresses 0x0000–0x005F of program memory
RAM. The monitor next attempts to boot load from an external
SROM or E
2
PROM on SPORT1 using the three wire connec-
tion of Figure 4. The monitor program first toggles the RFS1/
SROM
pin of the ADMC300 to reset the serial memory device.
If an SROM or E
2
PROM is connected to SPORT1, data is
clocked into the ADMC300 at a rate CLKOUT/26. Both
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