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参数资料
型号： ADMC300-ADVEVALKIT
厂商： Analog Devices, Inc.
元件分类： 圆形连接器
英文描述： Circular Connector; No. of Contacts:13; Series:MS27497; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:10; Circular Contact Gender:Socket; Circular Shell Style:Wall Mount Receptacle RoHS Compliant: No
中文描述： 高性能基于DSP的电机控制器
文件页数： 17/42页
文件大小： 297K
代理商： ADMC300-ADVEVALKIT
ADMC300
–17–
REV. B
cleared so that both the modulators and the decimation filters
come up in the normal mode. It is recommended that prior to
use, a full reset be performed.
ADC Registers
The composition of all the data registers associated with the ADC
system of the ADMC300 is shown at the end of the data sheet.
The reset values are shown for certain bits, where appropriate.
THREE-PHASE PWM CONTROLLER
The PWM generator block of the ADMC300 is a flexible,
programmable, three-phase PWM waveform generator that can
be programmed to generate the required switching patterns to
drive a three-phase voltage source inverter for ac induction
(ACIM) or permanent magnet synchronous (PMSM) motor
control. In addition, the PWM block contains special functions
that considerably simplify the generation of the required PWM
switching patterns for control of the electronically commutated
motor (ECM) or brushless dc motor (BDCM).
The PWM generator produces three pairs of PWM signals on
the six PWM output pins (AH, AL, BH, BL, CH and CL).
The six PWM output signals consist of three high side drive
signals (AH, BH and CH) and three low side drive signals (AL,
BL and CL). The polarity of the generated PWM signals may
be programmed by the PWMPOL pin, so that either active HI
or active LO PWM patterns can be produced by the ADMC300.
The switching frequency, dead time and minimum pulsewidths
of the generated PWM patterns are programmable using re-
spectively the PWMTM, PWMDT and PWMPD registers. In
addition, three duty-cycle control registers (PWMCHA,
PWMCHB and PWMCHC) directly control the duty cycles of
the three pairs of PWM signals.
Each of the six PWM output signals can be enabled or disabled
by separate output enable bits of the PWMSEG register. In
addition, three control bits of the PWMSEG register permit
crossover of the two signals of a PWM pair for easy control of
ECM or BDCM. In crossover mode, the PWM signal destined
for the high side switch is diverted to the complementary low-
side output and the signal destined for the low side switch is
diverted to the corresponding high side output signal.
In many applications, there is a need to provide an isolation
barrier in the gate-drive circuits that turn on the power devices
of the inverter. In general, there are two common isolation
techniques, optical isolation using opto-couplers and trans-
former isolation using pulse transformers. The PWM controller
of the ADMC300 permits mixing of the output PWM signals
with a high frequency chopping signal to permit easy interface
to such pulse transformers. The features of this gate-drive
chopping mode can be controlled by the PWMGATE register.
There is an 8-bit value within the PWMGATE register that
directly controls the chopping frequency. In addition, high
frequency chopping can be independently enabled for the high
side and the low side outputs using separate control bits in the
PWMGATE register.
The PWM generator is capable of operating in two distinct
modes, single update mode or double update mode. In single
update mode the duty cycle values are programmable only once
per PWM period, so that the resultant PWM patterns are sym-
metrical about the midpoint of the PWM period. In the double
update mode, a second updating of the PWM duty cycle values
is implemented at the midpoint of the PWM period. In this
mode, it is possible to produce asymmetrical PWM patterns,
that produce lower harmonic distortion in three-phase PWM
inverters. This technique also permits closed loop controllers to
change the average voltage applied to the machine windings at a
faster rate and so permits faster closed loop bandwidths to
be achieved. The operating mode of the PWM block (single
or double update mode) is selected by a control bit in the
MODECTRL register.
The PWM generator of the ADMC300 also provides an output
pulse on the PWMSYNC pin that is synchronized to the PWM
switching frequency. In single update mode a PWMSYNC pulse
is produced at the start of each PWM period. In double update
mode, an additional PWMSYNC pulse is produced at the mid-
point of each PWM period. The width of the PWMSYNC pulse
is programmable through the PWMSYNCWT register.
The PWM signals produced by the ADMC300 can be shut off
in a number of different ways. First, there is a dedicated asyn-
chronous PWM shutdown pin,
PWMTRIP
, that, when brought
LO, instantaneously places all six PWM outputs in the OFF
state (as determined by the state of the PWMPOL pin). In addi-
tion, each of the PIO lines of the ADMC300 (PIO0 to PIO11)
can be configured to act as an additional PWM shutdown. By
setting the appropriate bit in the PIOPWM register, the corre-
sponding PIO line acts as an asynchronous PWM shutdown
source in a manner identical to the
PWMTRIP
pin. These two
hardware shutdown mechanisms are asynchronous so that the
associated PWM disable circuitry does not go through any
clocked logic, thereby ensuring correct PWM shutdown even in
the event of a loss of the DSP clock. In addition to the hardware
shutdown features, the PWM system may be shut down in soft-
ware by writing to the PWMSWT register.
Status information about the PWM system of the ADMC300 is
available to the user in the SYSSTAT register. In particular, the
state of both the
PWMTRIP
and the PWMPOL pins is avail-
able, as well as a status bit that indicates whether operation is in
the first half or the second half of the PWM period.
A functional block diagram of the PWM controller is shown in
Figure 11. The generation of the six output PWM signals on
pins AH to CL is controlled by four important blocks:
The Three-Phase PWM Timing Unit, which is the core of the
PWM controller, generates three pairs of complemented and
dead-time-adjusted center-based PWM signals.
The Output Control Unit allows the redirection of the outputs
of the Three-Phase Timing Unit for each channel to either the
high side or the low side output. In addition, the Output Con-
trol Unit allows individual enabling/disabling of each of the six
PWM output signals.
The Gate Drive Unit provides the correct polarity output
PWM signals based on the state of the PWMPOL pin. The
Gate Drive Unit also permits the generation of the high fre-
quency chopping frequency and its subsequent mixing with
the PWM signals.
The PWM Shutdown Controller takes care of the various
PWM shutdown modes (via the
PWMTRIP
pin, the PIO lines
or the PWMSWT register) and generates the correct
RESET
signal for the Timing Unit.
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