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| 型号： | ADMC300-ADVEVALKIT |
| 厂商： | Analog Devices, Inc. |
| 元件分类： | 圆形连接器 |
| 英文描述： | Circular Connector; No. of Contacts:13; Series:MS27497; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:10; Circular Contact Gender:Socket; Circular Shell Style:Wall Mount Receptacle RoHS Compliant: No |
| 中文描述： | 高性能基于DSP的电机控制器 |
| 文件页数： | 22/42页 |
| 文件大小： | 297K |
| 代理商： | ADMC300-ADVEVALKIT |
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ADMC300
–22–
REV. B
Typical PWM output signals with high frequency chopping
enabled on both high-side and low-side signals are shown in
Figure 15. Chopping of the high side PWM outputs (AH, BH
and CH) is enabled by setting Bit 8 of the PWMGATE regis-
ter. Chopping of the low-side PWM outputs (AL, BL and CL)
is enabled by setting Bit 9 of the PWMGATE register. The high
frequency chopping frequency is controlled by the 8-bit word
(GDCLK) placed in Bits 0 to 7 of the PWMGATE register.
The period of this high frequency carrier is:
(
T
GDCLK
t
CHOP
CK
=
×
+
)
[
]
×
4
1
and the chopping frequency is therefore an integral subdivision
of the CLKOUT frequency:
f
CHOP
=
f
CLKOUT
4
×
(
GDCLK
+
1)
[
]
The GDCLK value may range from 0 to 255, corresponding
to a programmable chopping frequency rate from 24.4 kHz to
6.25 MHz for a 25 MHz CLKOUT rate. The gate drive features
must be programmed before operation of the PWM controller
and typically are not changed during normal operation of the
PWM controller. Following a reset, all bits of the PWMGATE
register are cleared so that high frequency chopping is disabled,
by default.
PWMTM
PWMTM
[4
(GDCLK+1)
t
CK
]
2
PWMDT
2
PWMDT
PWMCHA
PWMCHA
AH
AL
Figure 15. Typical Active LO PWM Signals with High Fre-
quency Gate Chopping Enabled on Both High Side and
Low Side Switches (GDCLK is integer equivalent of value
in Bits 0 to 7 of PWMGATE register.)
PWM Polarity Control, PWMPOL Pin
The polarity of the PWM signals produced at the output pins
AH to CL may be selected in hardware by the PWMPOL pin.
Connecting the PWMPOL pin to GND selects active LO PWM
outputs, such that a LO level is interpreted as a command to
turn on the associated power device. Conversely, connecting
VDD to the PWMPOL pin selects active HI PWM and the
associated power devices are turned ON by a HI level at the
PWM outputs. There is an internal pull-up on the PWMPOL
pin, so that if this pin becomes disconnected (or is not con-
nected), active HI PWM will be produced. The level on the
PWMPOL pin may be read from Bit 2 of the SYSSTAT regis-
ter, where a zero indicates a measured LO level at the PWMPOL
pin.
PWM Shutdown
In the event of external fault conditions, it is essential that
the PWM system be instantaneously shut down in a safe
fashion. A low level on the
PWMTRIP
pin provides an in-
stantaneous, asynchronous (independent of the DSP clock)
shutdown of the PWM controller. All six PWM outputs are
placed in the OFF state (as defined by the PWMPOL pin).
In addition, the PWMSYNC pulse is disabled. The
PWMTRIP
pin has an internal pull-down resistor so that if the pin becomes
disconnected the PWM will be disabled. The state of the
PWMTRIP
pin can be read from Bit 0 of the SYSSTAT
register.
The 12 PIO lines of the ADMC300 can also be configured to
operate as PWM shutdown pins using the PIOPWM register.
The 12-bit PIOPWM has a control bit for each PIO line (Bit 0
controls PIO0 etc.). Setting the control bit enables the corre-
sponding PIO line as a PWM shutdown pin. A low level on the
PIO line will then generate an instantaneous, asynchronous
shutdown of the PWM system, in a manner identical to the
PWMTRIP
pin. On power-up, and following a reset, all PIO
lines are configured as inputs, have pull-downs and are pro-
grammed as PWM shutdown pins (PIOPWM = 0x0FFF) so
that the PWM is shut down. Correct operation of the PWM is
not possible without first correctly configuring the PIO system.
In addition, it is possible to initiate a PWM shutdown in soft-
ware by writing to the 1-bit read/write PWMSWT register.
The act of writing to this register sets the bit in the PWMSWT
register and generates a PWM shutdown command in a manner
identical to the
PWMTRIP
or PIO pins. A hardware trip has no
effect on the PWMSWT register. Following a PWM shutdown, it
is possible to read the PWMSWT register to determine if the
shutdown was generated by hardware or software. Reading the
PWMSWT register automatically clears its contents.
On the occurrence of a PWM shutdown command (either from
the
PWMTRIP
pin, the PIO lines or the PWMSWT register), a
PWMTRIP
interrupt will be generated. In addition, internal
timing of the three-phase timing unit of the PWM controller is
stopped. Following a PWM shutdown, the PWM can only be
re-enabled (in a
PWMTRIP
interrupt service routine, for ex-
ample) by writing to all of the PWMTM, PWMCHA, PWMCHB
and PWMCHC registers. Provided the external fault has been
cleared and the
PWMTRIP
or appropriate PIO lines have re-
turned to a HI level, internal timing of the three-phase timing
unit resumes and new duty-cycle values are latched on the next
PWMSYNC boundary.
PWM Registers
The configuration of all registers of the PWM system are shown
at the end of the data sheet.
ENCODER INTERFACE UNIT
The ADMC300 incorporates a powerful encoder interface block
to incremental shaft encoders, which are often used for position
feedback in high performance motion control systems. The en-
coder interface unit (EIU) includes a 16-bit quadrature up/down
counter and has three dedicated pins on the ADMC300. The
quadrature encoder signals are applied at the EIA and EIB pins
and the optional zero pulse may be applied at the EIZP pin. The
encoder interface unit will operate correctly with input frequen-
cies up to slightly less than a quarter of the CLKIN frequency
(3.1 MHz for a 12.5 MHz CLKIN). The direction of counting
of the quadrature counter is programmable. In addition, the
actual direction of counting may be read from the EIU status
register, EIUSTAT.
The EIU may be programmed to use the zero pulse to reset the
quadrature encoder, if required. Alternatively, the zero pulse
can be ignored and the encoder quadrature counter is reset
according to the contents of a maximum count register,
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