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参数资料
| 型号： | ADMC300-ADVEVALKIT |
| 厂商： | Analog Devices, Inc. |
| 元件分类： | 圆形连接器 |
| 英文描述： | Circular Connector; No. of Contacts:13; Series:MS27497; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:10; Circular Contact Gender:Socket; Circular Shell Style:Wall Mount Receptacle RoHS Compliant: No |
| 中文描述： | 高性能基于DSP的电机控制器 |
| 文件页数： | 4/42页 |
| 文件大小： | 297K |
| 代理商： | ADMC300-ADVEVALKIT |
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–4–
REV. B
ADMC300–SPECIFICATIONS
ENCODER INTERFACE UNIT
Parameter
Test Conditions
Min
Typ
Max
Unit
f
ENC, MAX
Maximum Encoder Pulse Rate
1
3.1
MHz
NOTES
1
Assumes perfect quadrature encoder signals.
Specifications subject to change without notice.
AUXILIARY PWM OUTPUTS
Parameter
Test Conditions
Min
Typ
Max
Unit
Resolution
Switching Frequency
8
48.8
Bits
kHz
f
AUXPWM
Specifications subject to change without notice.
TIMING PARAMETERS
(V
DD
= AV
DD
= 5 V
10%, GND = AGND = 0 V, T
AMB
= –40 C to +85 C, CLKIN = 12.5 MHz, unless
otherwise noted)
(V
DD
= AV
DD
= 5 V
10%, GND = AGND = 0 V, T
AMB
= –40 C to +85 C, CLKIN = 12.5 MHz, unless
otherwise noted)
Parameter
Min
Max
Unit
Clock Signals
t
CK
is defined as 0.5 t
CKI
. The ADMC300 uses an input clock with a frequency equal
to half the instruction rate; a 12.5 MHz input clock (which is equivalent to 80 ns)
yields a 40 ns processor cycle (equivalent to 25 MHz). t
CK
values within the range of
0.5 t
CKI
period should be substituted for all relevant timing parameters to obtain
specification value.
Example: t
CKH
= 0.5 t
CK
– 10 ns = 0.5 (40 ns) – 10 ns = 10 ns.
Timing Requirements
:
t
CKI
CLKIN Period
t
CKIL
CLKIN Width Low
t
CKIH
CLKIN Width High
Switching Characteristics
:
t
CKL
CLKOUT Width Low
t
CKH
CLKOUT Width High
t
CKOH
CLKIN High to CLKOUT High
80
20
20
150
ns
ns
ns
0.5 t
CK
– 10
0.5 t
CK
– 10
0
ns
ns
ns
20
Control Signals
Timing Requirement:
t
RSP
RESET
Width Low
5 t
CK1
ns
PWM Shutdown Signals
Timing Requirements:
t
PWMTPW
t
PIOPWM
PWMTRIP
Width Low
PIO Width Low
3 t
CK
3 t
CK
ns
ns
NOTES
1
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).
Specifications subject to change without notice.
CLKIN
CLKOUT
t
CKOH
t
CKH
t
CKI
t
CKIH
t
CKL
t
CKIL
Figure 1. Clock Signals
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