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参数资料
| 型号： | ADMC300-ADVEVALKIT |
| 厂商： | Analog Devices, Inc. |
| 元件分类： | 圆形连接器 |
| 英文描述： | Circular Connector; No. of Contacts:13; Series:MS27497; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:10; Circular Contact Gender:Socket; Circular Shell Style:Wall Mount Receptacle RoHS Compliant: No |
| 中文描述： | 高性能基于DSP的电机控制器 |
| 文件页数： | 30/42页 |
| 文件大小： | 297K |
| 代理商： | ADMC300-ADVEVALKIT |
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ADMC300
–30–
REV. B
SPORT1. Two control bits in the MODECTRL register control
the state of the SPORT1 pins by manipulating internal multi-
plexers in the ADMC300. The configuration of SPORT1 is
illustrated in Figure 19.
Bit 4 of the MODECTRL register (DR1SEL) selects between
the two data receive pins. Setting Bit 4 of MODECTRL con-
nects the DR1B pin to the internal data receive port DR1 of
SPORT1. Clearing Bit 4 connects DR1A to DR1.
Setting Bit 5 of the MODECTRL register (UARTEN) config-
ures the serial port for UART mode. In this mode, the DR1
and RFS1 pins of the internal serial port are connected to-
gether. Additionally, setting the UARTEN bit connects the
FL1 flag of the DSP to the external RFS1/
SROM
pin. In this
mode, this pin is intended to be used to reset the external serial
ROM device.
The monitor code in ROM automatically configures the SPORT1
pins during the boot sequence. Initially, the DR1SEL bit is
cleared and the UARTEN bit is set so that the ADMC300 first
attempts to perform a reset of the external memory device using
the RFS1/SROM pin. This is accomplished by toggling the
FL1 flag using the following code segment:
SROMRESET: SET FL1;
TOGGLE FL1;
TOGGLE FL1;
RTS;
If successful, data will be clocked from the external device in a
continuous stream. The start of the data stream is detected by
the serial port on the RFS1 pin, which is connected internally
to the DR1 pin in this mode. If the serial load is successful,
code is downloaded and execution begins at the start of user
program memory (address 0x0060). Following a synchronous
boot load, SPORT1 could be configured for normal synchro-
nous serial mode by setting the DR1SEL pin to select the DR1B
data receive pin and by clearing the UARTEN bit to return to
SPORT mode.
Failing a synchronous boot load, the ADMC300 monitor auto-
matically sets the DR1SEL bit to select the DR1B pin and
remains in UARTEN mode. The monitor code then waits for a
header byte that tells it with which of the other interfaces it is to
communicate. Obviously, if a debugger interface is required on
SPORT1, it is not possible to use SPORT1 as a general pur-
pose synchronous serial port. If such a serial port is required, it
is recommended that SPORT0 be used.
Flag Pins
The ADMC300 provides flag pins. The alternate configuration
of SPORT1 includes a Flag In (FI) and Flag Out (FO) pin.
This alternate configuration of SPORT1 is selected by Bit 10 of
the DSP system control register, SYSCNTL at data memory
address, 0x3FFF. In the alternate configuration, the DR1 pin
(either DR1A or DR1B depending on the state of the DR1SEL
bit) becomes the FI pin and the DT1 pin becomes the FO pin.
Additionally, RFS1 is configured as the
IRQ0
interrupt input
and TFS1 is configured as the
IRQ1
interrupt. The serial port
clock, SCLK1, is still available in the alternate configuration.
Following boot loading from a serial memory device, it is pos-
sible to reconfigure the SPORT1 to this alternate configuration.
However, if a debugger interface is used, this configuration is
not possible as the normal serial port pins are required for
debugger communications.
The ADMC300 also contains two software flags, FL1 and FL2.
These flags may be controlled in software and perform specific
functions on the ADMC300. The FL1 pin has already been
described and is used to perform a reset of the external memory
device via the RFS1/
SROM
pin. The FL2 flag is used specifi-
cally to perform a full peripheral reset of the chip (including the
watchdog timer). This is accomplished by toggling the FL2 flag
in software using the following code segment:
PRESET:
SET FL2:
TOGGLE FL2;
TOGGLE FL2;
RTS;
System Control Registers
The system controller includes two registers, the MODECTRL
register used to control the multiplexing of the SPORT1 pins
and PWM operating mode, and the SYSSTAT register that
displays various status information. The format of these registers
is shown at the end of the data sheet.
Bit 0 of the SYSSTAT register indicates the state of the
PWMTRIP
pin. If this bit is set, the
PWMTRIP
pin is high and
no PWM trip is occurring. If this bit is cleared, then the PWM
is shut down. Bit 1 of the SYSSTAT register is set following a
watchdog timeout. This bit is cleared in normal operation. Fi-
nally, Bit 2 indicates the status of the PWMPOL pin. If this bit
is set, the PWMPOL pin is high and active high PWM outputs
will be produced. Bit 3 indicates the half cycle in which the
PWM is operating.
Register Memory Map
The address, name, used bits and function of all motor control
peripheral registers of the ADMC300 are tabulated in Table
VIII. In addition, the relevant DSP core registers are tabulated
in Table IX. Full details of the DSP core registers can be ob-
tained by referring to the ADSP-2171 sections of the
ADSP-2100
Family User
’
s Manual, Third Edition.
Development Kit
To facilitate device evaluation and programming, an evaluation
kit (ADMC300-ADVEVALKIT) is available from Analog De-
vices. The evaluation kit consists of an evaluation board and
the Motion Control Debugger software. The evaluation kit
contains latest programming and device information. It is rec-
ommended that the evaluation kit be used for initial program
development.
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