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参数资料
| 型号： | ADMC300-ADVEVALKIT |
| 厂商： | Analog Devices, Inc. |
| 元件分类： | 圆形连接器 |
| 英文描述： | Circular Connector; No. of Contacts:13; Series:MS27497; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:10; Circular Contact Gender:Socket; Circular Shell Style:Wall Mount Receptacle RoHS Compliant: No |
| 中文描述： | 高性能基于DSP的电机控制器 |
| 文件页数： | 3/42页 |
| 文件大小： | 297K |
| 代理商： | ADMC300-ADVEVALKIT |
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–3–
REV. B
ADMC300
VOLTAGE REFERENCE
Parameter
Test Conditions
Min
Typ
Max
Unit
V
REF
Voltage Level
Source Current
2.25
2.75
–100
5
V
μ
A
mV/V
Power Supply Rejection Ratio (PSRR)
–5
Specifications subject to change without notice.
PULSEWIDTH MODULATOR
Parameter
Test Conditions
Min
Typ
Max
Unit
Counter Resolution
1
Edge Resolution
Programmable Dead Time
Programmable Dead Time Increments
Programmable Pulse Deletion
Programmable Deletion Increments
PWM Frequency Range
1
PWMSYNC Pulsewidth
Gate Drive Chop Frequency
16
Bits
ns
μ
s
ns
μ
s
ns
Hz
μ
s
MHz
Double Update Mode
40
T
D
0
81.84
80
T
MIN
0
40.92
40
f
PWM
T
SYNC
f
CHOP
191
0.04
0.0244
10.24
6.25
NOTES
1
Resolution varies with PWM switching frequency, 191 Hz = 16 bits, 3.05 kHz = 12 bits, 48.8 kHz = 8 bits (12.5 MHz CLKIN) in single update mode.
Specifications subject to change without notice.
(V
DD
= AV
DD
= 5 V 10%, GND = AGND = 0 V, V
REFIN
= 2.50 V, T
AMB
= –40 C to +85 C,
CLKIN = 12.5 MHz, unless otherwise noted)
(V
DD
= AV
DD
= 5 V
10%, GND = AGND = 0 V, T
AMB
= –40 C to +85 C, CLKIN = 12.5 MHz, unless
otherwise noted)
(V
DD
= AV
DD
= 5 V 10%, GND = AGND = 0 V, T
AMB
= –40 C to +85 C, CLKIN = 12.5 MHz, unless otherwise
noted)
ANALOG-TO-DIGITAL CONVERTER
Parameter
Signal-to-Noise Ratio
1
(SNR)
Total Harmonic Distortion
1
(THD)
Common-Mode Rejection Ratio
2
(CMRR)
Channel-Channel Crosstalk
3
Gain Error
Gain
V
IN
Analog Input Range
4
V
DIFF
Analog Input Voltage (Differential)
4
V
OFFSET
DC Offset Voltage
5
f
MOD, MAX
Maximum Sigma-Delta Modulator Rate
Test Conditions
Min
Typ
Max
Unit
@V
DD
= 5.0 V,
@ f
S
= 32.55 kHz,
@ f
IN
= 1.017 kHz,
ADCDIVn = 0x180,
V1–V5 = 4.0 V p-p
V1N–V5N = V
REFIN
= 2.5 V
72
76
dB
dB
dB
dB
%
LSB/V
V
V
mV
MHz
–70
–82
–76
5
10,600
0
V
DD
V
DD
/2
55
2.08
ADCDIVA = 0x180
ADCDIVB = 0x180
ADCDIVA = 0x180
ADCDIVB = 0x180
f
S, MAX
Maximum ADC Sample Rate
6
32.55
kHz
V
REFIN
R
IN
Reference Input Voltage
7
Equivalent Input Resistance
8
2.4
2.5
25
2.6
V
k
NOTES
1
SNR measured with ADC channel configured in single-ended mode. SNR measurement does not include harmonic distortion, THD includes first six harmonics.
The effective number of bits (ENOB) is related to the SNR by SNR = 6.02 (ENOB) +1.76 dB. Input signal filtered at 1.5 kHz.
2
Input signal applied to both pins of input differential pair of ADC channel.
3
Input signal applied to four ADC channels, dc applied to fifth, measurement taken at fifth ADC channel.
4
Peak-peak input voltage in differential input configuration is half that in single-ended mode.
5
This offset may be corrected for, using the ADC calibration feature.
6
At maximum sigma-delta modulator rate of 2.08 MHz.
7
Input reference pins: REFINA, REFINB.
8
Analog signal input pins: V1–V5, V1N–V5N.
Specifications subject to change without notice.
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