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| 型号： | ADMC300-ADVEVALKIT |
| 厂商： | Analog Devices, Inc. |
| 元件分类： | 圆形连接器 |
| 英文描述： | Circular Connector; No. of Contacts:13; Series:MS27497; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:10; Circular Contact Gender:Socket; Circular Shell Style:Wall Mount Receptacle RoHS Compliant: No |
| 中文描述： | 高性能基于DSP的电机控制器 |
| 文件页数： | 28/42页 |
| 文件大小： | 297K |
| 代理商： | ADMC300-ADVEVALKIT |
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ADMC300
–28–
REV. B
digital outputs using the PIODIR register. In this mode, writing
suitable patterns to the PIODATA register will trigger the
corresponding event capture on the ETU channels.
ETU Interrupt Generation
The completion of the event capture sequence can be defined as
either the occurrence of Event B or the second occurrence of
Event A by setting the appropriate bits of the ETUCONFIG
register. At the end of the capture sequence, the ETU gener-
ates an interrupt. For example, if Bit 2 of the ETUCONFIG
register is set, ETU Channel 0 will generate an ETU interrupt
on the occurrence of Event B on the ETU0 pin. On the other
hand, if Bit 6 of the ETUCONFIG register is cleared, ETU
Channel 1 will generate an ETU interrupt on the occurrence of
the second Event A on the ETU1 pin. Both ETU channels
generate the same interrupt to the DSP when capture is com-
plete. If both ETU channels are used simultaneously, the
ETUSTAT register can be polled to determine which caused
the interrupt. If capture on ETU Channel 0 is complete, Bit 0
of the ETUSTAT register is set; if capture on ETU Channel 1
is complete, Bit 1 is set. Reading the ETUSTAT register auto-
matically clears all bits of the register.
CLKIN
ETU0
ETU
INTERRUPT
ETU1
ETUDIVIDE (15
…
0)
EVENT
DETECTOR
EVENT
DETECTOR
ETUA0 (15
…
0)
ETUB0 (15
…
0)
ETUAA0 (15
…
0)
ETU Timer
ETUA1 (15
…
0)
ETUB1 (15
…
0)
ETUAA1 (15
…
0)
ETUCONFIG (7)
…
0
ETUCTRL (1
…
0)
ETUSTAT (1
…
0)
ETUTIME (15
…
0)
Figure 18. Functional Block Diagram of Event Timer Unit
ETU Operating Modes
The ETU channels of the ADMC300 can operate in two dis-
tinct modes; single shot and free-running. The particular mode
may be selected for ETU Channel 0 by programming Bit 3 of
the ETUCONFIG register and for ETU channel 1 by program-
ming Bit 7 of the ETUCONFIG register. Setting these bits
puts the respective ETU channel in free-running mode while
clearing the bits enables the single-shot mode. In single-shot
mode, upon completion of the capture sequence, further event
capture is disabled until the appropriate bit of the ETUCTRL
register has been set. Setting Bit 0 of the ETUCTRL register
restarts the capture for ETU Channel 0, while Bit 1 restarts
capture for Channel 1. In the free-running mode, the bits of the
ETUCTRL register remain set and the ETU channel continues
to capture following the generation of the interrupt.
ETU Registers
The configuration of the ETU registers is shown at the end of
the data sheet.
INTERRUPT CONTROL
Operation and control of the various interrupt sources is man-
aged by a combination of the internal interrupt controller of the
DSP core and a dedicated Programmable Interrupt Controller
(PIC) that manages all interrupts from the motor control peripher-
als. Eight internal DSP core interrupts comprise the peripheral
(
IRQ2
), SPORT0 transmit and receive, two software, SPORT1
transmit and receive (or alternatively
IRQ1
and
IRQ0
), and the
timer interrupts. The ADMC300 includes eleven additional
interrupts that are interfaced to the DSP core through the
IRQ2
interrupt. The eleven peripheral interrupts include two ADC
interrupts (one per bank), the PWMSYNC interrupt, the five
PIO interrupts (four dedicated to PIO0 to PIO3 and the com-
bined PIO4 to PIO11 interrupt), the EIU interrupt, the ETU
interrupt and the
PWMTRIP
interrupt. Each of the nineteen
interrupts of the ADMC300 has a dedicated four word sec-
tion in the interrupt vector table. The start address in the
interrupt vector table for each of the nineteen ADMC300
interrupt sources is tabulated in Table VII. The interrupts
are listed from the highest priority to the lowest priority.
The entire interrupt control system of the ADMC300 is config-
ured and controlled by the IFC, IMASK and ICNTL registers
of the DSP core and the PICMASK and PICVECTOR registers
of the PIC block.
Table VII. Interrupt Vector Addresses
Interrupt Vector
Address
Interrupt Source
Peripheral Interrupt (
IRQ2
)
ADC Bank A Update
PWMSYNC
ADC Bank B Update
PIO Interrupt (PIO4 to PIO11)
Encoder Interface Interrupt
Event Timer Unit Interrupt
PIO0 Interrupt
PIO1 Interrupt
PIO2 Interrupt
PIO3 Interrupt
PWMTRIP
Interrupt
SPORT0 Transmit Interrupt
SPORT0 Receive Interrupt
Software Interrupt 1
Software Interrupt 0
SPORT1 Transmit Interrupt or
IRQ1
SPORT1 Receive Interrupt or
IRQ0
Timer
0x0004 (Highest Priority)
0x0030
0x0034
0x0038
0x003C
0x0040
0x0044
0x0048
0x004C
0x0050
0x0054
0x0058
0x0010
0x0014
0x0018
0x001C
0x0020
0x0024
0x0028 (Lowest Priority)
Interrupt Masking
Interrupt masking (or disabling) is controlled by the IMASK
register of the DSP core and the PICMASK register. These
registers contain individual bits that must be set to enable the
various interrupt sources. It is important to remember that if
any peripheral interrupt is to be enabled both the
IRQ2
interrupt enable bit (Bit 9) of the IMASK register and the
appropriate bit of the PICMASK register must be set. The
configuration of both the IMASK and PICMASK registers of
the ADMC300 is shown at the end of the data sheet.
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