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参数资料
| 型号： | ADMCF328BR |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 0-BIT, 10 MHz, OTHER DSP, PDSO28 |
| 封装： | SOIC-28 |
| 文件页数： | 10/36页 |
| 文件大小： | 993K |
| 代理商： | ADMCF328BR |
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ADMCF328
–18–
REV. A
V1
PWMSYNC
VVIL
COMPARATOR
OUTPUT
t
TCRST
TPWM –TCRST
tVIL
VC
VCMAX
Figure 12. Analog Input Block Operation
The ADC system consists of four comparators and a single
timer, which may be clocked at either the DSP rate or half the
DSP rate, depending on the setting of the ADCCNT bit (Bit 7)
of the MODECTRL register. When this bit is cleared, the timers
count at a slower rate of CLKIN. When this bit is set, they count
at CLKOUT or twice the rate of CLKIN. ADC1, ADC2, ADC3,
and ADCAUX are the registers that capture the conversion
times, which are effectively the timer values, when the associated
comparator trips.
CHARGING CAPACITOR – nF
200
0
010
DECIMAL
COUNTS 100
150
50
246
8
Figure 13. PWMSYNCWT Program Value
ADC Resolution
The ADC is intrinsically linked to the PWM block through the
PWMSYNC pulse controlling the ADC conversion process.
Because of this link, the effective resolution of the ADC is a
function of both the PWM switching frequency and the rate
at which the ADC counter timer is clocked. For a CLKOUT
period of tCK and a PWM period of TPWM, the maximum count of
the ADC is given by:
Max Count
T
PWM
T
CRST
t
CK
for MODECTRL Bit
=
()
=
min 4095
2
71
,
Max Count
T
PWM
T
CRST
t
CK
for MODECTRL Bit
=
()
=
min
,
4095
71
Where TPWM is equal to the PWM period if operating in single
update mode, or it is equal to half that period if operating in
double update mode. For an assumed CLKOUT frequency of
20 MHz and PWMSYNC pulsewidth of 2.0
s, the effective
resolution of the ADC block is tabulated for various PWM
switching frequencies in Table VII.
Table VII. ADC Resolution Examples
PWM
MODECTRL[7] = 0
MODECTRL[7] = 1
Frequency
Max
Effective
Max
Effective
(kHz)
Count
Resolution
Count
Resolution
2.4
4095
12
4095
12
4
2480
>11
4095
12
8
1230
>10
2460
>11
18
535
>9
1070
>10
25
380
>8
760
>9
Charging Capacitor Selection
The charging capacitor value is selected based on the sample
(PWM) frequency desired. A too-small capacitor value will reduce
the available resolution of the ADC by having the ramp voltage
rise rapidly and convert too quickly, not utilizing all possible
counts available in the PWM cycle. Too large a capacitor may not
convert in the available PWM cycle returning 0x000. To select a
charging capacitor, use Figure 14, select the sampling frequency
desired, determine if the current source is to be tuned to a nominal
100
A or left in the default (0x0 code) trim state, then determine
the proper charge capacitor off the appropriate curve.
FREQUENCY – kHz
100
1
100
10
C
NOM
–
nF
10
TUNED ICONST
DEFAULT ICONST
Figure 14. Timing Capacitor Selection
Programmable Current Source
The ADMCF328 has an internal current source that is used to
charge an external capacitor, generating the voltage ramp used
for conversion. The magnitude of the output of the current
source circuit is subject to manufacturing variations and can
vary from one device to the next. Therefore, the ADMCF328
incudes a programmable current source whose output can always
be tuned to within 5% of the target 100
A. A 3-bit register,
ICONST_TRIM, allows the user to make this adjustment. The
output current is proportional to the value written to the regis-
ter: 0x0 produces the minimum output, and 0x7 produces the
maximum output. The default value of ICONST_TRIM after
reset is 0x0.
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