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参数资料
| 型号： | ADMCF328BR |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 0-BIT, 10 MHz, OTHER DSP, PDSO28 |
| 封装： | SOIC-28 |
| 文件页数： | 9/36页 |
| 文件大小： | 993K |
| 代理商： | ADMCF328BR |
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ADMCF328
–17–
REV. A
PWM Registers
The conguration of the PWM registers is described at the end
of the data sheet. The parameters of the PWM block are tabu-
lated in Table V.
ADC OVERVIEW
The ADC of the ADMCF328 is based upon the single slope
conversion technique. This approach offers an inherently
monotonic conversion process within the noise and stability of its
components, and there will be no missing codes.
Table VI. ADC Auxiliary Channel Selection
MODECTRL (1)
MODECTRL (0)
Select
ADCMUX1
ADCMUX0
VAUX0
0
VAUX1
0
1
VAUX2
1
0
Calibration (VREF)1
1
The single slope technique has been adapted on the ADMCF328
for four channels that are simultaneously converted. Refer to
Figure 11 for the functional schematic of the ADC. Two of the
main inputs (V1 and V2) are directly connected as high imped-
ance voltage inputs. The third main input channel (ISENSE) has
a special design to monitor the voltage on a current-sensing
resistor whose voltage is always below (more negative than)
the power supply rail. The fourth channel has been congured
with a serially connected 4-to-1 multiplexer. Table VI shows the
multiplexer input selection codes. One of these auxiliary
multiplexed channels is used to calibrate the ramp against the
internal voltage reference (VREF).
VAUX0
V2L
VAUXL
PWMSYNC (CONVST)
ADC
REGISTERS
V1L
V3L
V2
ISENSE
(CAP RESET)
CLK MODECTRL<7>
12-BIT
ADC
TIMER
BLOCK
PWMTRIP
VREF
COMP
ADC REGISTERS
ADC1
ADC2
ADC3
ADCAUX
MODECTRL<0..1>
EXTERNAL
CHARGING
CAP
VC
ICONST
ICONST_TRIM<2:0>
VAUX1
VAUX2
COMP
V1
COMP
–5
0.8
C
GND
4–1
MUX
Figure 11. ADC Overview
Comparing each ADC input to a reference ramp voltage and
timing the comparison of the two signals performs the conversion
process. The actual conversion point is the time point inter-
section of the input voltage and the ramp voltage (VC) as shown in
Figure 12. This time is converted to counts by the 12-bit ADC
Timer Block and is stored in the ADC registers. The ramp voltage
used to perform the conversion is generated by driving a xed
current into an off-chip capacitor, where the capacitor voltage is
VI C
t
C
=
() ×
Following reset, VC = 0 at t = 0. This reset and the start of
the conversion process are initiated by the PWMSYNC pulse,
as shown in Figure 12. The width of the PWMSYNC pulse is
controlled by the PWMSYNCWT register and should be pro-
grammed according to Figure 13 to ensure complete resetting.
In order to compensate for IC process manufacturing tolerances
(and to adjust for capacitor tolerances), the current source of the
ADMCF328 is software programmable. The software setting of the
magnitude of the ICONST current generator is accomplished by
selecting one of eight steps over approximately 20% current range.
Table V. Fundamental Characteristics of PWM Generation Unit of ADMCF328
16-BIT PWM TIMER
Parameter
Min
Typ
Max
Unit
Counter Resolution
16
Bits
Edge Resolution (Single Update Mode)
100
ns
Edge Resolution (Double Update Mode)
50
ns
Programmable Dead Time Range
0
100
s
Programmable Dead Time Increments
100
ns
Programmable Pulse Deletion Range
0
100
s
Programmable Pulse Deletion Increments
100
ns
PWM Frequency Range
150
Hz
PWMSYNC Pulsewidth (TCRST)
0.05
12.5
s
Gate Drive Chop Frequency Range
0.02
5
MHz
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