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参数资料
| 型号： | ADMCF328BR |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 0-BIT, 10 MHz, OTHER DSP, PDSO28 |
| 封装： | SOIC-28 |
| 文件页数： | 6/36页 |
| 文件大小： | 993K |
| 代理商： | ADMCF328BR |
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ADMCF328
–14–
REV. A
PWMCHA
2
PWMDT
PWMSYNCWT + 1
PWMCHA
PWMTM
AH
AL
PWMSYNC
SYSSTAT (3)
2
PWMDT
Figure 7. Typical PWM Outputs of Three-Phase Timing
Unit in Single Update Mode
Each switching edge is moved by an equal amount (PWMDT
× t
CK) to preserve the symmetrical output patterns. The PWMSYNC
pulse, whose width is set by the PWMSYNCWT register, is also
shown. Bit 3 of the SYSSTAT register indicates which half cycle
is active. This can be useful in double update mode, as will be
discussed later.
The resultant on-times of the PWM signals shown in Figure 7
may be written as:
TPWMCHA
PWMDT
t
TPWMTM
PWMCHA
PWMDT
t
AH
CK
AL
CK
=×
×
=×
×
2
(–
)
(–
–
)
The corresponding duty cycles are:
d
T
PWMCHA
PWMDT
PWMTM
d
T
PWMTM
PWMCHA
PWMDT
PWMTM
AH
S
AL
S
==
–
––
Obviously, negative values of TAH and TAL are not permitted
because the minimum permissible value is zero, corresponding
to a 0% duty cycle. In a similar fashion, the maximum value is
TS, corresponding to a 100% duty cycle.
The output signals from the timing unit for operation in double
update mode are shown in Figure 8. This illustrates a completely
general case where the switching frequency, dead time and duty
cycle are all changed in the second half of the PWM period. Of
course, the same value for any or all of these quantities could be
used in both halves of the PWM cycle. However, it can be seen
that there is no guarantee that symmetrical PWM signals will be
produced by the timing unit in this double update mode. Addi-
tionally, it is seen that the dead time is inserted into the PWM
signals in the same way as in the single update mode.
PWMCHA2
PWMSYNCWT2 + 1
PWMCHA1
PWMTM1
PWMTM2
PWMSYNCWT1 + 1
AH
AL
PWMSYNC
SYSSTAT (3)
2
PWMDT1
2
PWMDT2
Figure 8. Typical PWM Outputs of Three-Phase Timing
Unit in Double Update Mode
In general, the on-times of the PWM signals in double update
mode are dened by:
T
PWMCHA
PWMDT
t
AH
CK
=+
() ×
12
1
2
T
PWMTM
PWMCHA
PWMDT
t
AL
CK
=
+
×
12
1
21
2
where the subscript 1 refers to the value of that register during
the rst half cycle and the subscript 2 refers to the value during
the second half cycle. The corresponding duty cycles are:
d
T
PWMCHA
PWMTM
PWMDT
PWMTM
d
T
PWMTM
PWMCHA
PWMTM
PWMCHA
PWMDT
PWMTM
AH
S
AL
S
=
+
+
=
++
()
+
++
()
+
12
1
12
212
12
–
because for the completely general case in double update mode,
the switching period is given by:
TPWMTM
PWMTM
t
SCK
=+
() ×
12
Again, the values of TAH and TAL are constrained to lie between
zero and TS.
PWM signals similar to those illustrated in Figure 7 and Figure
8 can be produced on the BH, BL, CH, and CL outputs by pro-
gramming the PWMCHB and PWMCHC registers in a manner
identical to that described for PWMCHA.
The PWM controller does not produce any PWM outputs until
all of the PWMTM, PWMCHA, PWMCHB, and PWMCHC
registers have been written to at least once. After these registers
have been written, the counters in the three-phase timing unit
are enabled. Writing to these registers also starts the main PWM
timer. If during initialization, the PWMTM register is written
before the PWMCHA, PWMCHB, and PWMCHC registers,
the rst PWMSYNC pulse (and interrupt if enabled) will be gener-
ated (1.5
× t
CK
× PWMTM) seconds after the initial write to the
PWMTM register in single update mode. In double update mode,
the rst PWMSYNC pulse will be generated (tCK
× PWMTM)
seconds after the initial write to the PWMTM register in single
update mode.
Effective PWM Resolution
In single update mode, the same values of PWMCHA, PWMCHB
and PWMCHC are used to dene the on-times in both half
cycles of the PWM period. As a result, the effective resolution of
the PWM generation process is 2 tCK (or 100 ns for a 20 MHz
CLKOUT) since incrementing one of the duty cycle registers by
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