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参数资料
| 型号： | ADMCF328BR |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 0-BIT, 10 MHz, OTHER DSP, PDSO28 |
| 封装： | SOIC-28 |
| 文件页数： | 13/36页 |
| 文件大小： | 993K |
| 代理商： | ADMCF328BR |
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ADMCF328
–20–
REV. A
LOWER TRANSISTOR
CONDUCTION
UPPER
DIODE
CONDUCTION
LOWER TRANSISTOR
CONDUCTION
PWMSYNC
t
IBUS
IWINDING
VWINDING
Figure 17. Bus Current Signals
The auxiliary PWM system of the ADMCF328 can operate in
two different modes: independent mode or offset mode. The
operating mode of the auxiliary PWM system is controlled
by Bit 8 of the MODECTRL register. Setting Bit 8 of the
MODECTRL register places the auxiliary PWM system in the
independent mode. In this mode, the two auxiliary PWM genera-
tors are completely independent and separate switching
frequencies and duty cycles may be programmed for each aux-
iliary PWM output. In this mode, the 8-bit AUXTM0 register
sets the switching frequency of the signal at the AUX0 output
pin. Similarly, the 8-bit AUXTM1 register sets the switching
frequency of the signal at the AUX1 pin. The fundamental time
increment for the auxiliary PWM outputs is twice the DSP
instruction rate (or 2 tCK) and the corresponding switching
periods are given by:
T
AUXTM
t
AUX
CK
0
20
1
=×
+
() ×
T
AUXTM
t
AUX
CK
1
21 1
=×
+
() ×
Since the values in both AUXTM0 and AUXTM1 can range from
0 to 0xFF, the achievable switching frequency of the auxiliary PWM
signals may range from 39.1 kHz to 10 MHz for a CLKOUT
frequency of 20 MHz.
The on-time of the two auxiliary PWM signals is programmed by
the two 8-bit AUXCH0 and AUXCH1 registers, according to:
T
AUXTM
t
ON
AUX
CK
,
0
20
=×
() ×
T
AUXTM
t
ON
AUX
CK
,
1
21
=×
() ×
so that output duty cycles from 0% to 100% are possible. Duty
cycles of 100% are produced if the on-time value exceeds the
period value. Typical auxiliary PWM waveforms in independent
mode are shown in Figure 18(a). When Bit 8 of the MODECTRL
register is cleared, the auxiliary PWM channels are placed in offset
mode. In offset mode, the switching frequency of the two signals
on the AUX0 and AUX1 pins are identical and controlled by
AUXTM0 in a manner similar to that previously described for
independent mode. In addition, the on times of both the AUX0
and AUX1 signals are controlled by the AUXCH0 and AUXCH1
registers as before. However, in this mode the AUXTM1 register
denes the offset time from the rising edge of the signal on the
AUX0 pin to that on the AUX1 pin according to:
T
AUXTM
t
OFFSET
CK
=×
+
() ×
21 1
For correct operation in this mode, the value written to the
AUXTM1 register must be less than the value written to the
AUXTM0 register. Typical auxiliary PWM waveforms in offset
mode are shown in Figure 18(b). Again, duty cycles from 0% to
100% are possible in this mode.
In both operating modes, the resolution of the auxiliary PWM
system is eight bits only at the minimum switching frequency
(AUXTM0 = AUXTM1 = 255 in independent mode, AUXTM0
= 255 in offset mode). Obviously, as the switching frequency is
increased, the resolution is reduced.
Values can be written to the auxiliary PWM registers at any
time. However, new duty cycle values written to the AUXCH0 and
AUXCH1 registers only become effective at the start of the next
cycle. Writing to the AUXTM0 or AUXTM1 registers causes
the internal timers to be reset to 0 and new PWM cycles to begin.
By default following a reset, Bit 8 of the MODECTRL register
is cleared, thus enabling offset mode. In addition, the registers
AUXTM0 and AUXTM1 default to 0xFF, corresponding to
the minimum switching frequency and zero offset. The on-time
registers AUXCH0 and AUXCH1 default to 0x00.
Auxiliary PWM Interface, Registers, and Pins
The registers of the auxiliary PWM system are summarized at
the end of the data sheet.
AUX0
AUX1
2
(AUXTM0 + 1)
2
(AUXTM1 + 1)
2
AUXCH1
2
AUXCH1
2
AUXCH0
(a) Independent Mode
AUX0
AUX1
2
(AUXTM1 + 1)
2
(AUXTM0 + 1)
2
AUXCH0
2
(AUXTM0 + 1)
2
AUXCH1
(b) Offset Mode
Figure 18. Typical Auxiliary PWM Signals. (All Times in
Increments of tCK)
PWM DAC Equation
The auxiliary PWM output can be ltered in order to produce a low
frequency analog signal between 0 V to VDD. For example, a 2-pole
lter with a 1.2 kHz cutoff frequency will sufciently attenuate the
PWM carrier. Figure 19 shows how the lter would be applied.
C1
C2
R1
R2
R1 = R2 = 13k
C1 = C2 = 10nF
AUXPWM
Figure 19. Auxiliary PWM Output Filter
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| ADMCF328BR-REEL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
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