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参数资料
| 型号： | ADN2525ACPZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 12/16页 |
| 文件大小： | 0K |
| 描述： | IC LASER DRIVER 10.7GBPS 16LFCSP |
| 标准包装： | 1,500 |
| 类型： | 激光二极管驱动器（光纤） |
| 数据速率： | 10.7Gbps |
| 通道数： | 1 |
| 电源电压： | 3.07 V ~ 3.53 V |
| 电流 - 电源： | 39mA |
| 电流 - 调制： | 80mA |
| 电流 - 偏置： | 100mA |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 16-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 16-LFCSP-VQ |
| 包装： | 带卷 (TR) |
| 安装类型： | 表面贴装 |
ADN2525
VCC + 1.1V
IMODP, IMODN
used as heat sink, as shown in Figure 31. A compact optical
module is a complex thermal environment, and calculations of
device junction temperature using the package θ JA (junction-to-
ambient thermal resistance) do not yield accurate results.
NORMAL OPERATION REGION
THERMAL COMPOUND
MODULE CASE
VCC
T TOP
VCC – 1.1V
DIE
T J
THERMOCOUPLE
PACKAGE
T PAD
PCB
Figure 30. Allowable Range for the Voltage at IMODP and IMODN
COPPER PLANE
LOAD MISTERMINATION
Due to its excellent S22 performance, the ADN2525 can drive
differential loads that range from 5 Ω to 50 Ω. In practice, many
TOSAs have differential resistance less than 50 Ω. In this case,
with 50 Ω differential transmission lines connecting the
ADN2525 to the load, the load end of the transmission lines are
misterminated. This mistermination leads to signal reflections
back to the driver. The excellent back-termination in the
ADN2525 absorbs these reflections, preventing their reflection
back to the load. This enables excellent optical eye quality to be
achieved, even when the load end of the transmission lines is
significantly misterminated. The connection between the load
and the ADN2525 must be made with 50 Ω differential (25 Ω
single-ended) transmission lines so that the driver end of the
transmission lines is properly terminated.
VIAS
Figure 31. Typical Optical Module Structure
The following procedure can be used to estimate the IC
junction temperature:
? T TOP is the temperature at top of package in °C.
? T PAD is the temperature at package exposed paddle in °C.
? T J is the IC junction temperature in °C.
? P is the power dissipation in W.
? θ J-TOP is the thermal resistance from IC junction to package top.
? θ J-PAD is the thermal resistance from IC junction to package
exposed pad.
T TOP
POWER CONSUMPTION
θ J-TOP
T TOP
P = VCC × ? MSET + I SUPPLY ? + V IBIAS × IBIAS
The power dissipated by the ADN2525 is given by
? V ?
? 13.5 ?
P
θ J-PAD
T PAD
T PAD
P × ( θ J ? PAD × θ J ? TOP ) + T TOP × θ J ? PAD + T PAD × θ J ? TOP
θ J ? PAD + θ J ? TOP
P = VCC × ? MSET + I SUPPLY ? + × V IBIAS
where:
VCC is the power supply voltage.
IBIAS is the bias current generated by the ADN2525.
V MSET is the voltage applied to the MSET pin.
I SUPPLY is the sum of the current that flows into the VCC,
IMODP, and IMODN pins of the ADN2525 when
IBIAS = IMOD = 0 expressed in amps (see Table 1).
V IBIAS is the average voltage on the IBIAS pin.
Considering V BSET /IBIAS = 10 as the conversion factor from
V BSET to IBIAS, the dissipated power becomes
? V ? V BSET
? 13 . 5 ? 10
Figure 32. Electrical Model for Thermal Calculations
T TOP and T PAD can be determined by measuring the temperature
at points inside the module, as shown in Figure 31. The thermo-
couples should be positioned to obtain an accurate measurement
of the package top and paddle temperatures. Using the model
shown in Figure 32, the junction temperature can be calculated by
T J =
where:
P is the power dissipated by the ADN2525.
To ensure long-term reliable operation, the junction tempera-
ture of the ADN2525 must not exceed 125°C, as specified in
Rev. A | Page 12 of 16
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