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参数资料
| 型号： | ADN2525ACPZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/16页 |
| 文件大小： | 0K |
| 描述： | IC LASER DRIVER 10.7GBPS 16LFCSP |
| 标准包装： | 1,500 |
| 类型： | 激光二极管驱动器（光纤） |
| 数据速率： | 10.7Gbps |
| 通道数： | 1 |
| 电源电压： | 3.07 V ~ 3.53 V |
| 电流 - 电源： | 39mA |
| 电流 - 调制： | 80mA |
| 电流 - 偏置： | 100mA |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 16-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 16-LFCSP-VQ |
| 包装： | 带卷 (TR) |
| 安装类型： | 表面贴装 |
ADN2525
APPLICATIONS INFORMATION
TYPICAL APPLICATION CIRCUIT
The dc voltages applied to the BSET and MSET pins control the
bias and modulation currents. The bias current can be monitored
as a voltage drop across the 1 kΩ resistor connected between
the IBMON pin and GND. The ALS pin allows the user to turn
on/off the bias and modulation currents, depending on the logic
level applied to the pin. The data signal source must be connected
to the DATAP and DATAN pins of the ADN2525 using 50 Ω
transmission lines. The modulation current outputs, IMODP
and IMODN, must be connected to the load (TOSA) using 50 Ω
shows recommended components for the ac-coupling interface
between the ADN2525 and TOSA. For up-to-date component
recommendations, contact sales.
Working with a TOSA laser sample, the circuit in Figure 33 delivers
the optical performance shown in Figure 15 and Figure 16. For
additional applications information and optical eye performance of
other laser samples, contact ADI sales or see the ADN2525
application notes at www.analog.com .
Table 6.
LAYOUT GUIDELINES
Due to the high frequencies at which the ADN2525 operates,
care should be taken when designing the PCB layout to obtain
optimum performance. Controlled impedance transmission
lines must be used for the high speed signal paths. The length of
the transmission lines must be kept to a minimum to reduce
losses and pattern-dependent jitter. The PCB layout must be
symmetrical, both on the DATAP and DATAN inputs and on
the IMODP and IMODN outputs, to ensure a balance between
the differential signals. All VCC and GND pins must be connected
to solid copper planes by using low inductance connections.
When the connections are made through vias, multiple vias
can be connected in parallel to reduce the parasitic inductance.
Each GND pin must be locally decoupled with high quality
capacitors. If proper decoupling cannot be achieved using a
single capacitor, the user can use multiple capacitors in parallel
for each GND pin. A 20 μF tantalum capacitor must be used as a
general decoupling capacitor for the entire module. For guidelines
on the surface-mount assembly of the ADN2525, see Amkor
Technology? Application Notes for Surface Mount Assembly of
Amkor’s MicroLeadFrame? (MLF) Packages.
Component
R1, R2
R3, R4
C3, C4
L2, L3, L6, L7
L1, L4, L5, L8
Value
36 Ω
200 Ω
100 nF
82 nH
10 μH
Description
0603 size resistor
0603 size resistor
0603 size capacitor,
Phycomp 223878615649
0402 size inductor,
Murata LQW15AN82NJ0
0603 size inductor,
Murata LQM21FN100M70L
BSET
GND
TP1
R5
1k ?
GND
C5
10nF
VCC
L1
R1
L8
R4
VCC
BSET IBMON IBIAS GND
VCC
VCC
VCC
VCC
L2
L7
Z 0 = 50 ?
Z 0 = 25 ?
Z 0 = 25 ?
DATAP
DATAP
IMODP
Z 0 = 50 ?
C1
ADN2525
GND
Z 0 = 25 ?
C4
Z 0 = 25 ?
TOSA
DATAN
DATAN
IMODN
C2
GND
C3
VCC
VCC
VCC
VCC
L3
L6
MSET NC1
ALS
GND
VCC
MSET
3.3V
VCC
C7
200μF
ALS
C6
10nF
GND
L4
VCC
R2
L5
VCC
R3
GND
Figure 33. Typical ADN2525 Application Circuit
Rev. A | Page 13 of 16
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