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参数资料
| 型号： | ADN2525ACPZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 14/16页 |
| 文件大小： | 0K |
| 描述： | IC LASER DRIVER 10.7GBPS 16LFCSP |
| 标准包装： | 1,500 |
| 类型： | 激光二极管驱动器（光纤） |
| 数据速率： | 10.7Gbps |
| 通道数： | 1 |
| 电源电压： | 3.07 V ~ 3.53 V |
| 电流 - 电源： | 39mA |
| 电流 - 调制： | 80mA |
| 电流 - 偏置： | 100mA |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 16-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 16-LFCSP-VQ |
| 包装： | 带卷 (TR) |
| 安装类型： | 表面贴装 |
ADN2525
DESIGN EXAMPLE
This design example covers:
? Headroom calculations for IBIAS, IMODP, and IMODN pins.
? Calculation of the typical voltage required at the BSET and
MSET pins to produce the desired bias and modulation currents.
This design example assumes that the resistance of the TOSA is
25 Ω, the forward voltage of the laser at low current is V F = 1 V,
IBIAS = 40 mA, IMOD = 60 mA, and VCC = 3.3 V.
Headroom Calculations
To ensure proper device operation, the voltages on the IBIAS,
IMODP, and IMODN pins must meet the compliance voltage
the voltage at the IBIAS pin can be written as
V IBIAS = VCC ? V F ? ( IBIAS × R TOSA ) ? V LA
where:
VCC is the supply voltage.
V F is the forward voltage across the laser at low current.
Assuming V LB = 0 V and IMOD = 60 mA, the minimum voltage
at the modulation output pins is equal to
VCC ? ( IMOD × 25)/2 = VCC ? 0.75
VCC ? 0.75 > VCC ? 1.1 V , which satisfies the requirement
The maximum voltage at the modulation output pins is equal to
VCC + ( IMOD × 25)/2 = VCC + 0.75
VCC + 0.75 < VCC + 1.1 V , which satisfies the requirement
Headroom calculations must be repeated for the minimum and
maximum values of the required IBIAS and IMOD ranges to
ensure proper device operation over all operating conditions.
BSET and MSET Pin Voltage Calculation
To set the desired bias and modulation currents, the BSET and
MSET pins of the ADN2525 must be driven with the appropriate
dc voltage. The voltage range required at the BSET pin to generate
the required IBIAS range can be calculated using the BSET
voltage to IBIAS gain specified in Table 1. Assuming that
IBIAS = 40 mA and the typical IBIAS/V BSET ratio of 100 mA/V,
the BSET voltage is given by
R TOSA is the resistance of the TOSA.
V LA is the dc voltage drop across L5, L6, L7, and L8.
V BSET =
IBIAS (mA)
100 mA/V
=
40
100
= 0 . 4 V
V LB is the dc voltage drop across L1, L2, L3, and L4.
For proper operation, the minimum voltage at the IBIAS pin
should be greater than 0.6 V, as specified by the minimum
Assuming that the voltage drop across the 25 Ω transmission
The BSET voltage range can be calculated using the required
IBIAS range and the minimum and maximum BSET voltage to
The voltage required at the MSET pin to produce the desired
modulation current can be calculated using
lines is negligible and that V LA = 0 V, V F = 1 V, and IBIAS =
40 mA,
V MSET =
IMOD
K
V IBIAS = 3.3 ? 1 ? (0.04 × 25) = 1.3 V
V IBIAS = 1.3 V > 0.6 V , which satisfies the requirement
The maximum voltage at the IBIAS pin must be less than the
maximum IBIAS compliance specification as described by
V COMPLIANCE_MAX = VCC ? 0.75 ? 4.4 × IBIAS (A)
where K is the MSET voltage to IMOD ratio.
The value of K depends on the actual resistance of the TOSA.
It can be read using the plot shown in Figure 29. For a TOSA
resistance of 25 Ω, the typical value of K = 120 mA/V. Assuming
that IMOD = 60 mA and using the preceding equation, the
MSET voltage is given by
For this example:
V COMPLIANCE_MAX = VCC – 0.75 ? 4.4 × 0.04 = 2.53 V
V MSET =
IMOD (mA)
120 mA/V
=
60
120
= 0 . 5 V
V IBIAS = 1.3 V < 2.53 V , which satisfies the requirement
To calculate the headroom at the modulation current pins
(IMODP and IMODN), the voltage has a dc component equal
to VCC due to the ac-coupled configuration and a swing equal
to IMOD × 25 Ω. For proper operation of the ADN2525, the
The MSET voltage range can be calculated using the required
IMOD range and the minimum and maximum K values. These
can be obtained from the minimum and maximum curves in
voltage at each modulation output pin should be within the
Rev. A | Page 14 of 16
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